-- 
-- Program 
-- C:\CAO\EXEMPLAR\BIN\PC\FPGA.EXE C:\TEMP\ORIGINAL\LOGIC2.VHD C:\TEMP\RTL\LOGI
-- C2.VHD -COMMAND_FILE=C:\CAO\EXEMPLAR\BIN\PC\TMP9.$$$ 
-- Version V2.1.7
-- Definition of  LOGIC2
-- 
-- VHDL Concurrent Statements, created by
-- Exemplar Logic's CORE
--      Fri Nov 17 12:55:28 1995
-- 
-- 
-- 

library exemplar ;
use exemplar.exemplar_1164.all ;
library ieee ;
use ieee.std_logic_1164.all ;

entity LOGIC2 is
   port (
      A_3, A_2, A_1, A_0, B_3, B_2, B_1, B_0, COMP_IN_2, COMP_IN_1, 
      COMP_IN_0 : in std_logic ;
      COMP_OUT_2, COMP_OUT_1, COMP_OUT_0 : out std_logic) ;
end LOGIC2 ;

architecture exemplar of LOGIC2 is
   signal
      vh_1, vh_2, vh_3, vh_6, vh_7, vh_8, vh_9, vh_10, vh_11, vh_12, vh_13: 
   std_logic ;
 
begin
   COMP_OUT_2 <= (COMP_IN_2 and vh_3) or (vh_1) ;
   vh_1 <= (vh_6 and vh_8 and vh_10) or ( not vh_7 and vh_10) or ( not vh_11
      ) ;
   vh_2 <= (vh_7 and vh_9 and vh_11) or ( not vh_6 and vh_11) or ( not vh_10
      ) ;
   vh_3 <= ( not vh_1 and  not vh_2) ;
   COMP_OUT_1 <= (COMP_IN_1 and vh_3) ;
   COMP_OUT_0 <= (COMP_IN_0 and vh_3) or ( not vh_1 and vh_2) ;
   vh_6 <= (A_2) or ( not B_2) ;
   vh_7 <= ( not A_2) or (B_2) ;
   vh_8 <= ( not B_0 and A_0 and vh_12) or ( not vh_13) ;
   vh_9 <= (B_0 and  not A_0 and vh_13) or ( not vh_12) ;
   vh_10 <= (A_3) or ( not B_3) ;
   vh_11 <= ( not A_3) or (B_3) ;
   vh_12 <= (A_1) or ( not B_1) ;
   vh_13 <= ( not A_1) or (B_1) ;

end exemplar ;