-- 
-- Program 
-- C:\CAO\EXEMPLAR\BIN\PC\FPGA.EXE C:\TEMP\ORIGINAL\LOGIC13.VHD C:\TEMP\RTL\LOG
-- IC13.RTL -COMMAND_FILE=C:\CAO\EXEMPLAR\BIN\PC\TMP4.$$$ 
-- Version V2.1.7
-- Definition of  LOGIC13
-- 
-- VHDL Concurrent Statements, created by
-- Exemplar Logic's CORE
--      Fri Nov 17 12:54:48 1995
-- 
-- 
-- 

library exemplar ;
use exemplar.exemplar_1164.all ;
library ieee ;
use ieee.std_logic_1164.all ;

entity LOGIC13 is
   port (
      A, B, C : in std_logic ;
      Z : out std_logic) ;
end LOGIC13 ;

architecture exemplar of LOGIC13 is
 
begin
   Z <= (B and A) or (C) ;

end exemplar ;