-- 
-- Program 
-- C:\CAO\EXEMPLAR\BIN\PC\FPGA.EXE C:\TEMP\ORIGINAL\LOGIC12.VHD C:\TEMP\RTL\LOG
-- IC12.VHD -COMMAND_FILE=C:\CAO\EXEMPLAR\BIN\PC\TMP26.$$$ 
-- Version V2.1.7
-- Definition of  LOGIC12
-- 
-- VHDL Concurrent Statements, created by
-- Exemplar Logic's CORE
--      Fri Nov 17 12:55:22 1995
-- 
-- 
-- 

library exemplar ;
use exemplar.exemplar_1164.all ;
library ieee ;
use ieee.std_logic_1164.all ;

entity LOGIC12 is
   port (
      A_7, A_6, A_5, A_4, A_3, A_2, A_1, A_0, B_7, B_6, B_5, B_4, B_3, B_2, 
      B_1, B_0 : in std_logic ;
      S_7, S_6, S_5, S_4, S_3, S_2, S_1, S_0 : inout std_logic ;
      FAILED : out std_logic) ;
end LOGIC12 ;

architecture exemplar of LOGIC12 is
   signal
      SIr4_30, SIr4_31, SSr6_0, SSr7_1, SSr9_0, SSr10_1, S1r0_1, S1r0_0, 
      SIr15_30, SIr15_31, SSr17_0, SSr18_1, SSr20_0, SSr21_1, S2r1_1, S2r1_0, 
      SIr26_30, SIr26_31, SSr28_0, SSr29_1, SSr31_0, SSr32_1, RA_1, RA_0, 
      SIr39_30, SIr39_31, SSr41_0, SSr42_1, SSr44_0, SSr45_1, S1r35_1, 
      S1r35_0, SIr50_30, SIr50_31, SSr52_0, SSr53_1, SSr55_0, SSr56_1, 
      S2r36_1, S2r36_0, SIr61_30, SIr61_31, SSr63_0, SSr64_1, SSr66_0, 
      SSr67_1, RB_1, RB_0, SIr74_30, SIr74_31, SSr76_0, SSr77_1, SSr79_0, 
      SSr80_1, S1r70_1, S1r70_0, SIr85_30, SIr85_31, SSr87_0, SSr88_1, 
      SSr90_0, SSr91_1, S2r71_1, S2r71_0, SIr96_30, SIr96_31, SSr98_0, 
      SSr99_1, SSr101_0, SSr102_1, RS1_1, RS1_0, SIr107_30, SIr107_31, 
      SSr109_0, SSr110_1, SSr112_0, SSr113_1, RS2_1, RS2_0, vh_1, vh_2, vh_3, 
      vh_4, vh_5, SIr4_29, vh_6, vh_7, vh_8, vh_9, SIr15_29, vh_10, vh_11, 
      vh_12, vh_13, SIr26_29, vh_14, vh_15, vh_16, vh_17, SIr39_29, vh_18, 
      vh_19, vh_20, vh_21, SIr50_29, vh_22, vh_23, vh_24, vh_25, SIr61_29, 
      vh_26, vh_27, vh_28, vh_29, vh_30, vh_31, vh_32, vh_33, vh_34, vh_35, 
      vh_36, vh_37, vh_38, vh_39, vh_40, vh_41, vh_42, vh_43, vh_44, vh_45, 
      vh_46, vh_47, vh_48, vh_49, vh_50, vh_51, vh_52, vh_53, vh_54, 
      SIr74_29, vh_55, vh_56, vh_57, vh_58, SIr85_29, vh_59, vh_60, vh_61, 
      vh_62, SIr96_29, vh_63, vh_64, vh_65, vh_66, SIr107_29, vh_67, vh_68: 
   std_logic ;
 
begin
   FAILED <= ( not vh_1) ;
   SIr4_30 <= (A_1 and  not A_3 and  not vh_2) or ( not A_1 and A_3 and 
       not vh_2) or ( not A_1 and  not A_3 and vh_2) or (A_1 and A_3 and 
      vh_2) ;
   SIr4_31 <= (A_0 and  not A_2) or ( not A_0 and A_2) ;
   SSr6_0 <= ( not SIr4_30 and SIr4_31 and  not SIr4_29) ;
   SSr7_1 <= (SIr4_30 and  not SIr4_31 and  not SIr4_29) ;
   SSr9_0 <= ( not SIr4_30 and  not SIr4_31 and SIr4_29) ;
   SSr10_1 <= ( not SIr4_30 and SIr4_31 and SIr4_29) ;
   S1r0_1 <= (SSr10_1) or (SSr7_1) ;
   S1r0_0 <= (SSr9_0) or (SSr6_0) ;
   SIr15_30 <= (A_5 and  not A_7 and  not vh_6) or ( not A_5 and A_7 and 
       not vh_6) or ( not A_5 and  not A_7 and vh_6) or (A_5 and A_7 and 
      vh_6) ;
   SIr15_31 <= (A_4 and  not A_6) or ( not A_4 and A_6) ;
   SSr17_0 <= ( not SIr15_30 and SIr15_31 and  not SIr15_29) ;
   SSr18_1 <= (SIr15_30 and  not SIr15_31 and  not SIr15_29) ;
   SSr20_0 <= ( not SIr15_30 and  not SIr15_31 and SIr15_29) ;
   SSr21_1 <= ( not SIr15_30 and SIr15_31 and SIr15_29) ;
   S2r1_1 <= (SSr21_1) or (SSr18_1) ;
   S2r1_0 <= (SSr20_0) or (SSr17_0) ;
   SIr26_30 <= (S1r0_1 and  not S2r1_1 and  not vh_10) or ( not S1r0_1 and 
      S2r1_1 and  not vh_10) or ( not S1r0_1 and  not S2r1_1 and vh_10) or (
      S1r0_1 and S2r1_1 and vh_10) ;
   SIr26_31 <= (S1r0_0 and  not S2r1_0) or ( not S1r0_0 and S2r1_0) ;
   SSr28_0 <= ( not SIr26_30 and SIr26_31 and  not SIr26_29) ;
   SSr29_1 <= (SIr26_30 and  not SIr26_31 and  not SIr26_29) ;
   SSr31_0 <= ( not SIr26_30 and  not SIr26_31 and SIr26_29) ;
   SSr32_1 <= ( not SIr26_30 and SIr26_31 and SIr26_29) ;
   RA_1 <= (SSr32_1) or (SSr29_1) ;
   RA_0 <= (SSr31_0) or (SSr28_0) ;
   SIr39_30 <= (B_1 and  not B_3 and  not vh_14) or ( not B_1 and B_3 and 
       not vh_14) or ( not B_1 and  not B_3 and vh_14) or (B_1 and B_3 and 
      vh_14) ;
   SIr39_31 <= (B_0 and  not B_2) or ( not B_0 and B_2) ;
   SSr41_0 <= ( not SIr39_30 and SIr39_31 and  not SIr39_29) ;
   SSr42_1 <= (SIr39_30 and  not SIr39_31 and  not SIr39_29) ;
   SSr44_0 <= ( not SIr39_30 and  not SIr39_31 and SIr39_29) ;
   SSr45_1 <= ( not SIr39_30 and SIr39_31 and SIr39_29) ;
   S1r35_1 <= (SSr45_1) or (SSr42_1) ;
   S1r35_0 <= (SSr44_0) or (SSr41_0) ;
   SIr50_30 <= (B_5 and  not B_7 and  not vh_18) or ( not B_5 and B_7 and 
       not vh_18) or ( not B_5 and  not B_7 and vh_18) or (B_5 and B_7 and 
      vh_18) ;
   SIr50_31 <= (B_4 and  not B_6) or ( not B_4 and B_6) ;
   SSr52_0 <= ( not SIr50_30 and SIr50_31 and  not SIr50_29) ;
   SSr53_1 <= (SIr50_30 and  not SIr50_31 and  not SIr50_29) ;
   SSr55_0 <= ( not SIr50_30 and  not SIr50_31 and SIr50_29) ;
   SSr56_1 <= ( not SIr50_30 and SIr50_31 and SIr50_29) ;
   S2r36_1 <= (SSr56_1) or (SSr53_1) ;
   S2r36_0 <= (SSr55_0) or (SSr52_0) ;
   SIr61_30 <= (S1r35_1 and  not S2r36_1 and  not vh_22) or ( not S1r35_1
       and S2r36_1 and  not vh_22) or ( not S1r35_1 and  not S2r36_1 and 
      vh_22) or (S1r35_1 and S2r36_1 and vh_22) ;
   SIr61_31 <= (S1r35_0 and  not S2r36_0) or ( not S1r35_0 and S2r36_0) ;
   SSr63_0 <= ( not SIr61_30 and SIr61_31 and  not SIr61_29) ;
   SSr64_1 <= (SIr61_30 and  not SIr61_31 and  not SIr61_29) ;
   SSr66_0 <= ( not SIr61_30 and  not SIr61_31 and SIr61_29) ;
   SSr67_1 <= ( not SIr61_30 and SIr61_31 and SIr61_29) ;
   RB_1 <= (SSr67_1) or (SSr64_1) ;
   RB_0 <= (SSr66_0) or (SSr63_0) ;
   S_7 <= (A_7 and  not B_7 and  not vh_50) or ( not A_7 and B_7 and  not 
      vh_50) or ( not A_7 and  not B_7 and vh_50) or (A_7 and B_7 and vh_50)
    ;
   S_6 <= (A_6 and  not B_6 and  not vh_46) or ( not A_6 and B_6 and  not 
      vh_46) or ( not A_6 and  not B_6 and vh_46) or (A_6 and B_6 and vh_46)
    ;
   S_5 <= (A_5 and  not B_5 and  not vh_42) or ( not A_5 and B_5 and  not 
      vh_42) or ( not A_5 and  not B_5 and vh_42) or (A_5 and B_5 and vh_42)
    ;
   S_4 <= (A_4 and  not B_4 and  not vh_38) or ( not A_4 and B_4 and  not 
      vh_38) or ( not A_4 and  not B_4 and vh_38) or (A_4 and B_4 and vh_38)
    ;
   S_3 <= (A_3 and  not B_3 and  not vh_34) or ( not A_3 and B_3 and  not 
      vh_34) or ( not A_3 and  not B_3 and vh_34) or (A_3 and B_3 and vh_34)
    ;
   S_2 <= (A_2 and  not B_2 and  not vh_30) or ( not A_2 and B_2 and  not 
      vh_30) or ( not A_2 and  not B_2 and vh_30) or (A_2 and B_2 and vh_30)
    ;
   S_1 <= (A_1 and  not B_1 and  not vh_26) or ( not A_1 and B_1 and  not 
      vh_26) or ( not A_1 and  not B_1 and vh_26) or (A_1 and B_1 and vh_26)
    ;
   S_0 <= (A_0 and  not B_0) or ( not A_0 and B_0) ;
   SIr74_30 <= (S_1 and  not S_3 and  not vh_51) or ( not S_1 and S_3 and 
       not vh_51) or ( not S_1 and  not S_3 and vh_51) or (S_1 and S_3 and 
      vh_51) ;
   SIr74_31 <= (S_0 and  not S_2) or ( not S_0 and S_2) ;
   SSr76_0 <= ( not SIr74_30 and SIr74_31 and  not SIr74_29) ;
   SSr77_1 <= (SIr74_30 and  not SIr74_31 and  not SIr74_29) ;
   SSr79_0 <= ( not SIr74_30 and  not SIr74_31 and SIr74_29) ;
   SSr80_1 <= ( not SIr74_30 and SIr74_31 and SIr74_29) ;
   S1r70_1 <= (SSr80_1) or (SSr77_1) ;
   S1r70_0 <= (SSr79_0) or (SSr76_0) ;
   SIr85_30 <= (S_5 and  not S_7 and  not vh_55) or ( not S_5 and S_7 and 
       not vh_55) or ( not S_5 and  not S_7 and vh_55) or (S_5 and S_7 and 
      vh_55) ;
   SIr85_31 <= (S_4 and  not S_6) or ( not S_4 and S_6) ;
   SSr87_0 <= ( not SIr85_30 and SIr85_31 and  not SIr85_29) ;
   SSr88_1 <= (SIr85_30 and  not SIr85_31 and  not SIr85_29) ;
   SSr90_0 <= ( not SIr85_30 and  not SIr85_31 and SIr85_29) ;
   SSr91_1 <= ( not SIr85_30 and SIr85_31 and SIr85_29) ;
   S2r71_1 <= (SSr91_1) or (SSr88_1) ;
   S2r71_0 <= (SSr90_0) or (SSr87_0) ;
   SIr96_30 <= (S1r70_1 and  not S2r71_1 and  not vh_59) or ( not S1r70_1
       and S2r71_1 and  not vh_59) or ( not S1r70_1 and  not S2r71_1 and 
      vh_59) or (S1r70_1 and S2r71_1 and vh_59) ;
   SIr96_31 <= (S1r70_0 and  not S2r71_0) or ( not S1r70_0 and S2r71_0) ;
   SSr98_0 <= ( not SIr96_30 and SIr96_31 and  not SIr96_29) ;
   SSr99_1 <= (SIr96_30 and  not SIr96_31 and  not SIr96_29) ;
   SSr101_0 <= ( not SIr96_30 and  not SIr96_31 and SIr96_29) ;
   SSr102_1 <= ( not SIr96_30 and SIr96_31 and SIr96_29) ;
   RS1_1 <= (SSr102_1) or (SSr99_1) ;
   RS1_0 <= (SSr101_0) or (SSr98_0) ;
   SIr107_30 <= (RA_1 and  not RB_1 and  not vh_63) or ( not RA_1 and RB_1
       and  not vh_63) or ( not RA_1 and  not RB_1 and vh_63) or (RA_1 and 
      RB_1 and vh_63) ;
   SIr107_31 <= (RA_0 and  not RB_0) or ( not RA_0 and RB_0) ;
   SSr109_0 <= ( not SIr107_30 and SIr107_31 and  not SIr107_29) ;
   SSr110_1 <= (SIr107_30 and  not SIr107_31 and  not SIr107_29) ;
   SSr112_0 <= ( not SIr107_30 and  not SIr107_31 and SIr107_29) ;
   SSr113_1 <= ( not SIr107_30 and SIr107_31 and SIr107_29) ;
   RS2_1 <= (SSr113_1) or (SSr110_1) ;
   RS2_0 <= (SSr112_0) or (SSr109_0) ;
   vh_1 <= (vh_67 and vh_68) ;
   vh_2 <= (A_0 and A_2) ;
   vh_3 <= (A_1 and vh_2) ;
   vh_4 <= (A_1 and A_3) ;
   vh_5 <= (A_3 and vh_2) ;
   SIr4_29 <= (vh_5) or (vh_4) or (vh_3) ;
   vh_6 <= (A_4 and A_6) ;
   vh_7 <= (A_5 and vh_6) ;
   vh_8 <= (A_5 and A_7) ;
   vh_9 <= (A_7 and vh_6) ;
   SIr15_29 <= (vh_9) or (vh_8) or (vh_7) ;
   vh_10 <= (S1r0_0 and S2r1_0) ;
   vh_11 <= (S1r0_1 and vh_10) ;
   vh_12 <= (S1r0_1 and S2r1_1) ;
   vh_13 <= (S2r1_1 and vh_10) ;
   SIr26_29 <= (vh_13) or (vh_12) or (vh_11) ;
   vh_14 <= (B_0 and B_2) ;
   vh_15 <= (B_1 and vh_14) ;
   vh_16 <= (B_1 and B_3) ;
   vh_17 <= (B_3 and vh_14) ;
   SIr39_29 <= (vh_17) or (vh_16) or (vh_15) ;
   vh_18 <= (B_4 and B_6) ;
   vh_19 <= (B_5 and vh_18) ;
   vh_20 <= (B_5 and B_7) ;
   vh_21 <= (B_7 and vh_18) ;
   SIr50_29 <= (vh_21) or (vh_20) or (vh_19) ;
   vh_22 <= (S1r35_0 and S2r36_0) ;
   vh_23 <= (S1r35_1 and vh_22) ;
   vh_24 <= (S1r35_1 and S2r36_1) ;
   vh_25 <= (S2r36_1 and vh_22) ;
   SIr61_29 <= (vh_25) or (vh_24) or (vh_23) ;
   vh_26 <= (A_0 and B_0) ;
   vh_27 <= (A_1 and vh_26) ;
   vh_28 <= (A_1 and B_1) ;
   vh_29 <= (B_1 and vh_26) ;
   vh_30 <= (vh_29) or (vh_28) or (vh_27) ;
   vh_31 <= (A_2 and vh_30) ;
   vh_32 <= (A_2 and B_2) ;
   vh_33 <= (B_2 and vh_30) ;
   vh_34 <= (vh_33) or (vh_32) or (vh_31) ;
   vh_35 <= (A_3 and vh_34) ;
   vh_36 <= (A_3 and B_3) ;
   vh_37 <= (B_3 and vh_34) ;
   vh_38 <= (vh_37) or (vh_36) or (vh_35) ;
   vh_39 <= (A_4 and vh_38) ;
   vh_40 <= (A_4 and B_4) ;
   vh_41 <= (B_4 and vh_38) ;
   vh_42 <= (vh_41) or (vh_40) or (vh_39) ;
   vh_43 <= (A_5 and vh_42) ;
   vh_44 <= (A_5 and B_5) ;
   vh_45 <= (B_5 and vh_42) ;
   vh_46 <= (vh_45) or (vh_44) or (vh_43) ;
   vh_47 <= (A_6 and vh_46) ;
   vh_48 <= (A_6 and B_6) ;
   vh_49 <= (B_6 and vh_46) ;
   vh_50 <= (vh_49) or (vh_48) or (vh_47) ;
   vh_51 <= (S_0 and S_2) ;
   vh_52 <= (S_1 and vh_51) ;
   vh_53 <= (S_1 and S_3) ;
   vh_54 <= (S_3 and vh_51) ;
   SIr74_29 <= (vh_54) or (vh_53) or (vh_52) ;
   vh_55 <= (S_4 and S_6) ;
   vh_56 <= (S_5 and vh_55) ;
   vh_57 <= (S_5 and S_7) ;
   vh_58 <= (S_7 and vh_55) ;
   SIr85_29 <= (vh_58) or (vh_57) or (vh_56) ;
   vh_59 <= (S1r70_0 and S2r71_0) ;
   vh_60 <= (S1r70_1 and vh_59) ;
   vh_61 <= (S1r70_1 and S2r71_1) ;
   vh_62 <= (S2r71_1 and vh_59) ;
   SIr96_29 <= (vh_62) or (vh_61) or (vh_60) ;
   vh_63 <= (RA_0 and RB_0) ;
   vh_64 <= (RA_1 and vh_63) ;
   vh_65 <= (RA_1 and RB_1) ;
   vh_66 <= (RB_1 and vh_63) ;
   SIr107_29 <= (vh_66) or (vh_65) or (vh_64) ;
   vh_67 <= ( not RS1_1 and  not RS2_1) or (RS1_1 and RS2_1) ;
   vh_68 <= ( not RS1_0 and  not RS2_0) or (RS1_0 and RS2_0) ;

end exemplar ;