-- 
-- Program 
-- C:\CAO\EXEMPLAR\BIN\PC\FPGA.EXE C:\TEMP\ORIGINAL\LOGIC11.VHD C:\TEMP\RTL\LOG
-- IC11.VHD -COMMAND_FILE=C:\CAO\EXEMPLAR\BIN\PC\TMP25.$$$ 
-- Version V2.1.7
-- Definition of  LOGIC11
-- 
-- VHDL Concurrent Statements, created by
-- Exemplar Logic's CORE
--      Fri Nov 17 12:48:57 1995
-- 
-- 
-- 

library exemplar ;
use exemplar.exemplar_1164.all ;
library ieee ;
use ieee.std_logic_1164.all ;

entity LOGIC11 is
   port (
      A_7, A_6, A_5, A_4, A_3, A_2, A_1, A_0, B_7, B_6, B_5, B_4, B_3, B_2, 
      B_1, B_0, C_7, C_6, C_5, C_4, C_3, C_2, C_1, C_0, SA, SB, SC : in 
      std_logic ;
      Z_7, Z_6, Z_5, Z_4, Z_3, Z_2, Z_1, Z_0 : out std_logic) ;
end LOGIC11 ;

architecture exemplar of LOGIC11 is
 
begin
   Z_7 <= C_7 when (SC = '1')  else 'Z' ;
   Z_6 <= C_6 when (SC = '1')  else 'Z' ;
   Z_5 <= C_5 when (SC = '1')  else 'Z' ;
   Z_4 <= C_4 when (SC = '1')  else 'Z' ;
   Z_3 <= C_3 when (SC = '1')  else 'Z' ;
   Z_2 <= C_2 when (SC = '1')  else 'Z' ;
   Z_1 <= C_1 when (SC = '1')  else 'Z' ;
   Z_0 <= C_0 when (SC = '1')  else 'Z' ;
   Z_7 <= B_7 when (SB = '1')  else 'Z' ;
   Z_6 <= B_6 when (SB = '1')  else 'Z' ;
   Z_5 <= B_5 when (SB = '1')  else 'Z' ;
   Z_4 <= B_4 when (SB = '1')  else 'Z' ;
   Z_3 <= B_3 when (SB = '1')  else 'Z' ;
   Z_2 <= B_2 when (SB = '1')  else 'Z' ;
   Z_1 <= B_1 when (SB = '1')  else 'Z' ;
   Z_0 <= B_0 when (SB = '1')  else 'Z' ;
   Z_7 <= A_7 when (SA = '1')  else 'Z' ;
   Z_6 <= A_6 when (SA = '1')  else 'Z' ;
   Z_5 <= A_5 when (SA = '1')  else 'Z' ;
   Z_4 <= A_4 when (SA = '1')  else 'Z' ;
   Z_3 <= A_3 when (SA = '1')  else 'Z' ;
   Z_2 <= A_2 when (SA = '1')  else 'Z' ;
   Z_1 <= A_1 when (SA = '1')  else 'Z' ;
   Z_0 <= A_0 when (SA = '1')  else 'Z' ;

end exemplar ;