-- 
-- Program 
-- C:\CAO\EXEMPLAR\BIN\PC\FPGA.EXE C:\TEMP\ORIGINAL\LOGIC10.VHD C:\TEMP\RTL\LOG
-- IC10.RTL -COMMAND_FILE=C:\CAO\EXEMPLAR\BIN\PC\TMP24.$$$ 
-- Version V2.1.7
-- Definition of  LOGIC10
-- 
-- VHDL Concurrent Statements, created by
-- Exemplar Logic's CORE
--      Fri Nov 17 12:48:34 1995
-- 
-- 
-- 

library exemplar ;
use exemplar.exemplar_1164.all ;
library ieee ;
use ieee.std_logic_1164.all ;

entity LOGIC10 is
   port (
      A_7, A_6, A_5, A_4, A_3, A_2, A_1, A_0, B_7, B_6, B_5, B_4, B_3, B_2, 
      B_1, B_0, C_7, C_6, C_5, C_4, C_3, C_2, C_1, C_0, D_7, D_6, D_5, D_4, 
      D_3, D_2, D_1, D_0, S : in std_logic ;
      Z_7, Z_6, Z_5, Z_4, Z_3, Z_2, Z_1, Z_0 : out std_logic) ;
end LOGIC10 ;

architecture exemplar of LOGIC10 is
   signal
      CD_7, CD_6, CD_5, CD_4, CD_3, CD_2, CD_1, CD_0, AB_7, AB_6, AB_5, AB_4, 
      AB_3, AB_2, AB_1, AB_0, vh_8, vh_9, vh_10, vh_11, vh_12, vh_13, vh_14, 
      vh_15, vh_16, vh_17, vh_18, vh_19, vh_20, vh_21, vh_22, vh_23, vh_24, 
      vh_25, vh_26, vh_27, vh_28, vh_29, vh_30, vh_31, vh_32, vh_33, vh_34, 
      vh_35, vh_36, vh_37, vh_38, vh_39, vh_40, vh_41, vh_42, vh_43, vh_44, 
      vh_45, vh_46, vh_47, vh_48, vh_49, vh_50, vh_51, vh_52, vh_53, vh_54, 
      vh_55, vh_56, vh_57, vh_58, vh_59, vh_60, vh_61, vh_62, vh_63, vh_64, 
      vh_65, vh_66, vh_67, vh_68, vh_69, vh_70, vh_71, vh_72, vh_73: 
   std_logic ;
 
begin
   Z_7 <= (vh_16) or (vh_8) ;
   Z_6 <= (vh_17) or (vh_9) ;
   Z_5 <= (vh_18) or (vh_10) ;
   Z_4 <= (vh_19) or (vh_11) ;
   Z_3 <= (vh_20) or (vh_12) ;
   Z_2 <= (vh_21) or (vh_13) ;
   Z_1 <= (vh_22) or (vh_14) ;
   Z_0 <= (vh_23) or (vh_15) ;
   CD_7 <= (C_7 and  not D_7 and  not vh_48) or ( not C_7 and D_7 and  not 
      vh_48) or ( not C_7 and  not D_7 and vh_48) or (C_7 and D_7 and vh_48)
    ;
   CD_6 <= (C_6 and  not D_6 and  not vh_44) or ( not C_6 and D_6 and  not 
      vh_44) or ( not C_6 and  not D_6 and vh_44) or (C_6 and D_6 and vh_44)
    ;
   CD_5 <= (C_5 and  not D_5 and  not vh_40) or ( not C_5 and D_5 and  not 
      vh_40) or ( not C_5 and  not D_5 and vh_40) or (C_5 and D_5 and vh_40)
    ;
   CD_4 <= (C_4 and  not D_4 and  not vh_36) or ( not C_4 and D_4 and  not 
      vh_36) or ( not C_4 and  not D_4 and vh_36) or (C_4 and D_4 and vh_36)
    ;
   CD_3 <= (C_3 and  not D_3 and  not vh_32) or ( not C_3 and D_3 and  not 
      vh_32) or ( not C_3 and  not D_3 and vh_32) or (C_3 and D_3 and vh_32)
    ;
   CD_2 <= (C_2 and  not D_2 and  not vh_28) or ( not C_2 and D_2 and  not 
      vh_28) or ( not C_2 and  not D_2 and vh_28) or (C_2 and D_2 and vh_28)
    ;
   CD_1 <= (C_1 and  not D_1 and  not vh_24) or ( not C_1 and D_1 and  not 
      vh_24) or ( not C_1 and  not D_1 and vh_24) or (C_1 and D_1 and vh_24)
    ;
   CD_0 <= (C_0 and  not D_0) or ( not C_0 and D_0) ;
   AB_7 <= (A_7 and  not B_7 and  not vh_73) or ( not A_7 and B_7 and  not 
      vh_73) or ( not A_7 and  not B_7 and vh_73) or (A_7 and B_7 and vh_73)
    ;
   AB_6 <= (A_6 and  not B_6 and  not vh_69) or ( not A_6 and B_6 and  not 
      vh_69) or ( not A_6 and  not B_6 and vh_69) or (A_6 and B_6 and vh_69)
    ;
   AB_5 <= (A_5 and  not B_5 and  not vh_65) or ( not A_5 and B_5 and  not 
      vh_65) or ( not A_5 and  not B_5 and vh_65) or (A_5 and B_5 and vh_65)
    ;
   AB_4 <= (A_4 and  not B_4 and  not vh_61) or ( not A_4 and B_4 and  not 
      vh_61) or ( not A_4 and  not B_4 and vh_61) or (A_4 and B_4 and vh_61)
    ;
   AB_3 <= (A_3 and  not B_3 and  not vh_57) or ( not A_3 and B_3 and  not 
      vh_57) or ( not A_3 and  not B_3 and vh_57) or (A_3 and B_3 and vh_57)
    ;
   AB_2 <= (A_2 and  not B_2 and  not vh_53) or ( not A_2 and B_2 and  not 
      vh_53) or ( not A_2 and  not B_2 and vh_53) or (A_2 and B_2 and vh_53)
    ;
   AB_1 <= (A_1 and  not B_1 and  not vh_49) or ( not A_1 and B_1 and  not 
      vh_49) or ( not A_1 and  not B_1 and vh_49) or (A_1 and B_1 and vh_49)
    ;
   AB_0 <= (A_0 and  not B_0) or ( not A_0 and B_0) ;
   vh_8 <= ( not S and CD_7) ;
   vh_9 <= ( not S and CD_6) ;
   vh_10 <= ( not S and CD_5) ;
   vh_11 <= ( not S and CD_4) ;
   vh_12 <= ( not S and CD_3) ;
   vh_13 <= ( not S and CD_2) ;
   vh_14 <= ( not S and CD_1) ;
   vh_15 <= ( not S and CD_0) ;
   vh_16 <= (S and AB_7) ;
   vh_17 <= (S and AB_6) ;
   vh_18 <= (S and AB_5) ;
   vh_19 <= (S and AB_4) ;
   vh_20 <= (S and AB_3) ;
   vh_21 <= (S and AB_2) ;
   vh_22 <= (S and AB_1) ;
   vh_23 <= (S and AB_0) ;
   vh_24 <= (C_0 and D_0) ;
   vh_25 <= (C_1 and vh_24) ;
   vh_26 <= (C_1 and D_1) ;
   vh_27 <= (D_1 and vh_24) ;
   vh_28 <= (vh_27) or (vh_26) or (vh_25) ;
   vh_29 <= (C_2 and vh_28) ;
   vh_30 <= (C_2 and D_2) ;
   vh_31 <= (D_2 and vh_28) ;
   vh_32 <= (vh_31) or (vh_30) or (vh_29) ;
   vh_33 <= (C_3 and vh_32) ;
   vh_34 <= (C_3 and D_3) ;
   vh_35 <= (D_3 and vh_32) ;
   vh_36 <= (vh_35) or (vh_34) or (vh_33) ;
   vh_37 <= (C_4 and vh_36) ;
   vh_38 <= (C_4 and D_4) ;
   vh_39 <= (D_4 and vh_36) ;
   vh_40 <= (vh_39) or (vh_38) or (vh_37) ;
   vh_41 <= (C_5 and vh_40) ;
   vh_42 <= (C_5 and D_5) ;
   vh_43 <= (D_5 and vh_40) ;
   vh_44 <= (vh_43) or (vh_42) or (vh_41) ;
   vh_45 <= (C_6 and vh_44) ;
   vh_46 <= (C_6 and D_6) ;
   vh_47 <= (D_6 and vh_44) ;
   vh_48 <= (vh_47) or (vh_46) or (vh_45) ;
   vh_49 <= (A_0 and B_0) ;
   vh_50 <= (A_1 and vh_49) ;
   vh_51 <= (A_1 and B_1) ;
   vh_52 <= (B_1 and vh_49) ;
   vh_53 <= (vh_52) or (vh_51) or (vh_50) ;
   vh_54 <= (A_2 and vh_53) ;
   vh_55 <= (A_2 and B_2) ;
   vh_56 <= (B_2 and vh_53) ;
   vh_57 <= (vh_56) or (vh_55) or (vh_54) ;
   vh_58 <= (A_3 and vh_57) ;
   vh_59 <= (A_3 and B_3) ;
   vh_60 <= (B_3 and vh_57) ;
   vh_61 <= (vh_60) or (vh_59) or (vh_58) ;
   vh_62 <= (A_4 and vh_61) ;
   vh_63 <= (A_4 and B_4) ;
   vh_64 <= (B_4 and vh_61) ;
   vh_65 <= (vh_64) or (vh_63) or (vh_62) ;
   vh_66 <= (A_5 and vh_65) ;
   vh_67 <= (A_5 and B_5) ;
   vh_68 <= (B_5 and vh_65) ;
   vh_69 <= (vh_68) or (vh_67) or (vh_66) ;
   vh_70 <= (A_6 and vh_69) ;
   vh_71 <= (A_6 and B_6) ;
   vh_72 <= (B_6 and vh_69) ;
   vh_73 <= (vh_72) or (vh_71) or (vh_70) ;

end exemplar ;