-- 
-- Program 
-- C:\CAO\EXEMPLAR\BIN\PC\FPGA.EXE C:\TEMP\ORIGINAL\LOGIC1.VHD C:\TEMP\RTL\LOGI
-- C1.RTL -COMMAND_FILE=C:\CAO\EXEMPLAR\BIN\PC\TMP23.$$$ 
-- Version V2.1.7
-- Definition of  LOGIC1
-- 
-- VHDL Concurrent Statements, created by
-- Exemplar Logic's CORE
--      Fri Nov 17 12:48:05 1995
-- 
-- 
-- 

library exemplar ;
use exemplar.exemplar_1164.all ;
library ieee ;
use ieee.std_logic_1164.all ;

entity LOGIC1 is
   port (
      A_3, A_2, A_1, A_0, B_3, B_2, B_1, B_0 : in std_logic ;
      Z_3, Z_2, Z_1, Z_0 : out std_logic) ;
end LOGIC1 ;

architecture exemplar of LOGIC1 is
   signal
      vh_4, vh_5, vh_6, vh_7, vh_8, vh_9, vh_10, vh_11, vh_12, vh_13, vh_14, 
      vh_15, vh_16, vh_17, vh_18, vh_19, vh_20, vh_21, vh_22, vh_23, vh_24: 
   std_logic ;
 
begin
   Z_3 <= (vh_9) or (vh_5) ;
   Z_2 <= (vh_10) or (vh_6) ;
   Z_1 <= (vh_11) or (vh_7) ;
   Z_0 <= (vh_12) or (vh_8) ;
   vh_4 <= (vh_24) or (vh_23) or (vh_22) ;
   vh_5 <= (B_3 and  not vh_4) ;
   vh_6 <= (B_2 and  not vh_4) ;
   vh_7 <= (B_1 and  not vh_4) ;
   vh_8 <= (B_0 and  not vh_4) ;
   vh_9 <= (A_3 and vh_4) ;
   vh_10 <= (A_2 and vh_4) ;
   vh_11 <= (A_1 and vh_4) ;
   vh_12 <= (A_0 and vh_4) ;
   vh_13 <= (A_0 and  not B_0) ;
   vh_14 <= (A_1 and  not B_1) ;
   vh_15 <= (A_1 and vh_13) ;
   vh_16 <= ( not B_1 and vh_13) ;
   vh_17 <= (vh_16) or (vh_15) or (vh_14) ;
   vh_18 <= (A_2 and  not B_2) ;
   vh_19 <= (A_2 and vh_17) ;
   vh_20 <= ( not B_2 and vh_17) ;
   vh_21 <= (vh_20) or (vh_19) or (vh_18) ;
   vh_22 <= (A_3 and  not B_3) ;
   vh_23 <= (A_3 and vh_21) ;
   vh_24 <= ( not B_3 and vh_21) ;

end exemplar ;