-- 
-- Program 
-- C:\CAO\EXEMPLAR\BIN\PC\FPGA.EXE C:\TEMP\ORIGINAL\LOGIC0.VHD C:\TEMP\RTL\LOGI
-- C0.RTL -COMMAND_FILE=C:\CAO\EXEMPLAR\BIN\PC\TMP22.$$$ 
-- Version V2.1.7
-- Definition of  LOGIC0
-- 
-- VHDL Concurrent Statements, created by
-- Exemplar Logic's CORE
--      Fri Nov 17 12:47:07 1995
-- 
-- 
-- 

library exemplar ;
use exemplar.exemplar_1164.all ;
library ieee ;
use ieee.std_logic_1164.all ;

entity LOGIC0 is
   port (
      A_3, A_2, A_1, A_0, B_3, B_2, B_1, B_0, C_3, C_2, C_1, C_0 : in 
      std_logic ;
      Z_3, Z_2, Z_1, Z_0 : out std_logic) ;
end LOGIC0 ;

architecture exemplar of LOGIC0 is
   signal
      vh_0, vh_1, vh_2, vh_3: std_logic ;
 
begin
   vh_0 <= (A_3 and B_3) ;
   vh_1 <= (A_2 and B_2) ;
   vh_2 <= (A_1 and B_1) ;
   vh_3 <= (A_0 and B_0) ;
   Z_3 <= (C_3) or (vh_0) ;
   Z_2 <= (C_2) or (vh_1) ;
   Z_1 <= (C_1) or (vh_2) ;
   Z_0 <= (C_0) or (vh_3) ;

end exemplar ;