-- 
-- Program 
-- C:\CAO\EXEMPLAR\BIN\PC\FPGA.EXE C:\TEMP\ORIGINAL\COUNT7.VHD C:\TEMP\RTL\COUN
-- T7.RTL -COMMAND_FILE=C:\CAO\EXEMPLAR\BIN\PC\TMP21.$$$ 
-- Version V2.1.7
-- Definition of  COUNT7
-- 
-- VHDL Concurrent Statements, created by
-- Exemplar Logic's CORE
--      Fri Nov 17 12:45:19 1995
-- 
-- 
-- 

library exemplar ;
use exemplar.exemplar_1164.all ;
library ieee ;
use ieee.std_logic_1164.all ;

entity COUNT7 is
   port (
      CLOCK, RESET : in std_logic ;
      DIVIDE_OUT : out std_logic) ;
end COUNT7 ;

architecture exemplar of COUNT7 is
   signal
      COUNT_3, COUNT_2, COUNT_1, COUNT_0, vh_1, vh_2, vh_3, vh_4, vh_5, vh_6, 
      vh_7, vh_8, vh_9, vh_10, vh_11, vh_12, vh_13, vh_14, vh_30, vh_31, 
      vh_32, vh_33: std_logic ;
 
begin
   vh_1 <= ( not COUNT_3 and  not vh_33) or (COUNT_3 and vh_33) ;
   vh_2 <= ( not COUNT_2 and  not vh_31) or (COUNT_2 and vh_31) ;
   vh_3 <= ( not COUNT_1 and  not COUNT_0) or (COUNT_1 and COUNT_0) ;
   vh_4 <= ( not COUNT_3 and  not COUNT_2 and  not COUNT_1 and  not COUNT_0)
    ;
   vh_5 <= ( not RESET and  not vh_4) ;
   vh_6 <= (vh_1 and vh_5) ;
   vh_7 <= (vh_6) or (vh_4) ;
   vh_8 <= ( not RESET and  not vh_4) ;
   vh_9 <= (vh_2 and vh_8) ;
   vh_10 <= (vh_9) or (vh_4) ;
   vh_11 <= ( not RESET and  not vh_4) ;
   vh_12 <= (vh_3 and vh_11) ;
   vh_13 <= ( not RESET and  not vh_4) ;
   vh_14 <= ( not COUNT_0 and vh_13) ;
   vh_30 <= (COUNT_1 and COUNT_0) ;
   vh_31 <= (vh_30) or (COUNT_0) or (COUNT_1) ;
   vh_32 <= (COUNT_2 and vh_31) ;
   vh_33 <= (vh_32) or (vh_31) or (COUNT_2) ;
   DFF( vh_7, CLOCK, COUNT_3) ;
   DFF( vh_10, CLOCK, COUNT_2) ;
   DFF( vh_12, CLOCK, COUNT_1) ;
   DFF( vh_14, CLOCK, COUNT_0) ;
   DFF( vh_4, CLOCK, DIVIDE_OUT) ;

end exemplar ;