-- 
-- Program 
-- C:\CAO\EXEMPLAR\BIN\PC\FPGA.EXE C:\TEMP\ORIGINAL\COUNT5.VHD C:\TEMP\RTL\COUN
-- T5.RTL -COMMAND_FILE=C:\CAO\EXEMPLAR\BIN\PC\TMP19.$$$ 
-- Version V2.1.7
-- Definition of  COUNT5
-- 
-- VHDL Concurrent Statements, created by
-- Exemplar Logic's CORE
--      Fri Nov 17 12:44:25 1995
-- 
-- 
-- 

library exemplar ;
use exemplar.exemplar_1164.all ;
library ieee ;
use ieee.std_logic_1164.all ;

entity COUNT5 is
   port (
      CLOCK, RESET : in std_logic ;
      COUNT_OUT_7, COUNT_OUT_6, COUNT_OUT_5, COUNT_OUT_4, COUNT_OUT_3, 
      COUNT_OUT_2, COUNT_OUT_1, COUNT_OUT_0 : inout std_logic) ;
end COUNT5 ;

architecture exemplar of COUNT5 is
   signal
      vh_8, vh_9, vh_10, vh_11, vh_12, vh_13, vh_14, vh_15, vh_16, vh_17, 
      vh_18, vh_19, vh_20, vh_21, vh_22, vh_23, vh_24, vh_25, vh_26, vh_27, 
      vh_28, vh_29, vh_30, vh_31, vh_32, vh_33: std_logic ;
 
begin
   vh_8 <= (COUNT_OUT_0 and  not RESET) ;
   vh_9 <= (COUNT_OUT_7 and  not RESET) ;
   vh_10 <= (COUNT_OUT_6 and  not RESET) ;
   vh_11 <= (COUNT_OUT_5 and  not RESET) ;
   vh_12 <= (COUNT_OUT_4 and  not RESET) ;
   vh_13 <= (COUNT_OUT_3 and  not RESET) ;
   vh_14 <= (COUNT_OUT_2 and  not RESET) ;
   vh_15 <= (COUNT_OUT_1 and  not RESET) ;
   vh_16 <= (vh_8) or (RESET) ;
   vh_17 <= ( not RESET) or (RESET) ;
   vh_18 <= (COUNT_OUT_7 and  not vh_17) ;
   vh_19 <= (vh_18) or (vh_16) ;
   vh_20 <= (COUNT_OUT_6 and  not vh_17) ;
   vh_21 <= (vh_20) or (vh_9) ;
   vh_22 <= (COUNT_OUT_5 and  not vh_17) ;
   vh_23 <= (vh_22) or (vh_10) ;
   vh_24 <= (COUNT_OUT_4 and  not vh_17) ;
   vh_25 <= (vh_24) or (vh_11) ;
   vh_26 <= (COUNT_OUT_3 and  not vh_17) ;
   vh_27 <= (vh_26) or (vh_12) ;
   vh_28 <= (COUNT_OUT_2 and  not vh_17) ;
   vh_29 <= (vh_28) or (vh_13) ;
   vh_30 <= (COUNT_OUT_1 and  not vh_17) ;
   vh_31 <= (vh_30) or (vh_14) ;
   vh_32 <= (COUNT_OUT_0 and  not vh_17) ;
   vh_33 <= (vh_32) or (vh_15) ;
   DFF( vh_19, CLOCK, COUNT_OUT_7) ;
   DFF( vh_21, CLOCK, COUNT_OUT_6) ;
   DFF( vh_23, CLOCK, COUNT_OUT_5) ;
   DFF( vh_25, CLOCK, COUNT_OUT_4) ;
   DFF( vh_27, CLOCK, COUNT_OUT_3) ;
   DFF( vh_29, CLOCK, COUNT_OUT_2) ;
   DFF( vh_31, CLOCK, COUNT_OUT_1) ;
   DFF( vh_33, CLOCK, COUNT_OUT_0) ;

end exemplar ;