-- 
-- Program 
-- C:\CAO\EXEMPLAR\BIN\PC\FPGA.EXE C:\TEMP\ORIGINAL\COUNT2.VHD C:\TEMP\RTL\COUN
-- T2.RTL -COMMAND_FILE=C:\CAO\EXEMPLAR\BIN\PC\TMP16.$$$ 
-- Version V2.1.7
-- Definition of  COUNT2
-- 
-- VHDL Concurrent Statements, created by
-- Exemplar Logic's CORE
--      Fri Nov 17 12:43:12 1995
-- 
-- 
-- 

library exemplar ;
use exemplar.exemplar_1164.all ;
library ieee ;
use ieee.std_logic_1164.all ;

entity COUNT2 is
   port (
      CLOCK, RESET : in std_logic ;
      COUNT_OUT_7, COUNT_OUT_6, COUNT_OUT_5, COUNT_OUT_4, COUNT_OUT_3, 
      COUNT_OUT_2, COUNT_OUT_1, COUNT_OUT_0 : inout std_logic) ;
end COUNT2 ;

architecture exemplar of COUNT2 is
   signal
      vh_8, vh_9, vh_10, vh_11, vh_12, vh_13, vh_14, vh_15, vh_16, vh_17, 
      vh_18, vh_19, vh_20, vh_21, vh_22, vh_47, vh_48, vh_49, vh_50, vh_51, 
      vh_52: std_logic ;
 
begin
   vh_8 <= (COUNT_OUT_7 and  not vh_52) or ( not COUNT_OUT_7 and vh_52) ;
   vh_9 <= (COUNT_OUT_6 and  not vh_51) or ( not COUNT_OUT_6 and vh_51) ;
   vh_10 <= (COUNT_OUT_5 and  not vh_50) or ( not COUNT_OUT_5 and vh_50) ;
   vh_11 <= (COUNT_OUT_4 and  not vh_49) or ( not COUNT_OUT_4 and vh_49) ;
   vh_12 <= (COUNT_OUT_3 and  not vh_48) or ( not COUNT_OUT_3 and vh_48) ;
   vh_13 <= (COUNT_OUT_2 and  not vh_47) or ( not COUNT_OUT_2 and vh_47) ;
   vh_14 <= (COUNT_OUT_1 and  not COUNT_OUT_0) or ( not COUNT_OUT_1 and 
      COUNT_OUT_0) ;
   vh_15 <= ( not RESET and vh_8) ;
   vh_16 <= ( not RESET and vh_9) ;
   vh_17 <= ( not RESET and vh_10) ;
   vh_18 <= ( not RESET and vh_11) ;
   vh_19 <= ( not RESET and vh_12) ;
   vh_20 <= ( not RESET and vh_13) ;
   vh_21 <= ( not RESET and vh_14) ;
   vh_22 <= ( not COUNT_OUT_0 and  not RESET) ;
   vh_47 <= (COUNT_OUT_1 and COUNT_OUT_0) ;
   vh_48 <= (COUNT_OUT_2 and vh_47) ;
   vh_49 <= (COUNT_OUT_3 and vh_48) ;
   vh_50 <= (COUNT_OUT_4 and vh_49) ;
   vh_51 <= (COUNT_OUT_5 and vh_50) ;
   vh_52 <= (COUNT_OUT_6 and vh_51) ;
   DFF( vh_15, CLOCK, COUNT_OUT_7) ;
   DFF( vh_16, CLOCK, COUNT_OUT_6) ;
   DFF( vh_17, CLOCK, COUNT_OUT_5) ;
   DFF( vh_18, CLOCK, COUNT_OUT_4) ;
   DFF( vh_19, CLOCK, COUNT_OUT_3) ;
   DFF( vh_20, CLOCK, COUNT_OUT_2) ;
   DFF( vh_21, CLOCK, COUNT_OUT_1) ;
   DFF( vh_22, CLOCK, COUNT_OUT_0) ;

end exemplar ;