-- 
-- Program 
-- C:\CAO\EXEMPLAR\BIN\PC\FPGA.EXE C:\TEMP\ORIGINAL\COUNT1.VHD C:\TEMP\RTL\COUN
-- T1.RTL -COMMAND_FILE=C:\CAO\EXEMPLAR\BIN\PC\TMP15.$$$ 
-- Version V2.1.7
-- Definition of  COUNT1
-- 
-- VHDL Concurrent Statements, created by
-- Exemplar Logic's CORE
--      Fri Nov 17 12:42:43 1995
-- 
-- 
-- 

library exemplar ;
use exemplar.exemplar_1164.all ;
library ieee ;
use ieee.std_logic_1164.all ;

entity COUNT1 is
   port (
      CLOCK, RESET : in std_logic ;
      COUNT_OUT_7, COUNT_OUT_6, COUNT_OUT_5, COUNT_OUT_4, COUNT_OUT_3, 
      COUNT_OUT_2, COUNT_OUT_1, COUNT_OUT_0 : inout std_logic) ;
end COUNT1 ;

architecture exemplar of COUNT1 is
   signal
      vh_8, vh_9, vh_10, vh_11, vh_12, vh_13, vh_14, vh_15, vh_16, vh_22, 
      vh_28, vh_34, vh_40, vh_46, vh_52, vh_58, vh_64, vh_65, vh_66, vh_67, 
      vh_68, vh_69: std_logic ;
 
begin
   vh_8 <= (COUNT_OUT_7 and  not vh_69) or ( not COUNT_OUT_7 and vh_69) ;
   vh_9 <= (COUNT_OUT_6 and  not vh_68) or ( not COUNT_OUT_6 and vh_68) ;
   vh_10 <= (COUNT_OUT_5 and  not vh_67) or ( not COUNT_OUT_5 and vh_67) ;
   vh_11 <= (COUNT_OUT_4 and  not vh_66) or ( not COUNT_OUT_4 and vh_66) ;
   vh_12 <= (COUNT_OUT_3 and  not vh_65) or ( not COUNT_OUT_3 and vh_65) ;
   vh_13 <= (COUNT_OUT_2 and  not vh_64) or ( not COUNT_OUT_2 and vh_64) ;
   vh_14 <= (COUNT_OUT_1 and  not COUNT_OUT_0) or ( not COUNT_OUT_1 and 
      COUNT_OUT_0) ;
   vh_15 <= ( not COUNT_OUT_0) ;
   vh_16 <= '0' ;
   vh_22 <= '0' ;
   vh_28 <= '0' ;
   vh_34 <= '0' ;
   vh_40 <= '0' ;
   vh_46 <= '0' ;
   vh_52 <= '0' ;
   vh_58 <= '0' ;
   vh_64 <= (COUNT_OUT_1 and COUNT_OUT_0) ;
   vh_65 <= (COUNT_OUT_2 and vh_64) ;
   vh_66 <= (COUNT_OUT_3 and vh_65) ;
   vh_67 <= (COUNT_OUT_4 and vh_66) ;
   vh_68 <= (COUNT_OUT_5 and vh_67) ;
   vh_69 <= (COUNT_OUT_6 and vh_68) ;
   DFFPC( vh_8, vh_16, RESET, CLOCK, COUNT_OUT_7) ;
   DFFPC( vh_9, vh_22, RESET, CLOCK, COUNT_OUT_6) ;
   DFFPC( vh_10, vh_28, RESET, CLOCK, COUNT_OUT_5) ;
   DFFPC( vh_11, vh_34, RESET, CLOCK, COUNT_OUT_4) ;
   DFFPC( vh_12, vh_40, RESET, CLOCK, COUNT_OUT_3) ;
   DFFPC( vh_13, vh_46, RESET, CLOCK, COUNT_OUT_2) ;
   DFFPC( vh_14, vh_52, RESET, CLOCK, COUNT_OUT_1) ;
   DFFPC( vh_15, vh_58, RESET, CLOCK, COUNT_OUT_0) ;

end exemplar ;