-- 
-- Program 
-- C:\CAO\EXEMPLAR\BIN\PC\FPGA.EXE C:\TEMP\ORIGINAL\COUNT0.VHD C:\TEMP\RTL\COUN
-- T0.RTL -COMMAND_FILE=C:\CAO\EXEMPLAR\BIN\PC\TMP14.$$$ 
-- Version V2.1.7
-- Definition of  COUNT0
-- 
-- VHDL Concurrent Statements, created by
-- Exemplar Logic's CORE
--      Fri Nov 17 12:41:54 1995
-- 
-- 
-- 

library exemplar ;
use exemplar.exemplar_1164.all ;
library ieee ;
use ieee.std_logic_1164.all ;

entity COUNT0 is
   port (
      CLOCK : in std_logic ;
      COUNT_OUT_7, COUNT_OUT_6, COUNT_OUT_5, COUNT_OUT_4, COUNT_OUT_3, 
      COUNT_OUT_2, COUNT_OUT_1, COUNT_OUT_0 : inout std_logic) ;
end COUNT0 ;

architecture exemplar of COUNT0 is
   signal
      vh_8, vh_9, vh_10, vh_11, vh_12, vh_13, vh_14, vh_15, vh_40, vh_41, 
      vh_42, vh_43, vh_44, vh_45: std_logic ;
 
begin
   vh_8 <= (COUNT_OUT_7 and  not vh_45) or ( not COUNT_OUT_7 and vh_45) ;
   vh_9 <= (COUNT_OUT_6 and  not vh_44) or ( not COUNT_OUT_6 and vh_44) ;
   vh_10 <= (COUNT_OUT_5 and  not vh_43) or ( not COUNT_OUT_5 and vh_43) ;
   vh_11 <= (COUNT_OUT_4 and  not vh_42) or ( not COUNT_OUT_4 and vh_42) ;
   vh_12 <= (COUNT_OUT_3 and  not vh_41) or ( not COUNT_OUT_3 and vh_41) ;
   vh_13 <= (COUNT_OUT_2 and  not vh_40) or ( not COUNT_OUT_2 and vh_40) ;
   vh_14 <= (COUNT_OUT_1 and  not COUNT_OUT_0) or ( not COUNT_OUT_1 and 
      COUNT_OUT_0) ;
   vh_15 <= ( not COUNT_OUT_0) ;
   vh_40 <= (COUNT_OUT_1 and COUNT_OUT_0) ;
   vh_41 <= (COUNT_OUT_2 and vh_40) ;
   vh_42 <= (COUNT_OUT_3 and vh_41) ;
   vh_43 <= (COUNT_OUT_4 and vh_42) ;
   vh_44 <= (COUNT_OUT_5 and vh_43) ;
   vh_45 <= (COUNT_OUT_6 and vh_44) ;
   DFF( vh_8, CLOCK, COUNT_OUT_7) ;
   DFF( vh_9, CLOCK, COUNT_OUT_6) ;
   DFF( vh_10, CLOCK, COUNT_OUT_5) ;
   DFF( vh_11, CLOCK, COUNT_OUT_4) ;
   DFF( vh_12, CLOCK, COUNT_OUT_3) ;
   DFF( vh_13, CLOCK, COUNT_OUT_2) ;
   DFF( vh_14, CLOCK, COUNT_OUT_1) ;
   DFF( vh_15, CLOCK, COUNT_OUT_0) ;

end exemplar ;