SPARC instruction simulator (sis-3.0.1, 10-09-1998)
SIS is a SPARC instruction simulator developed at ESTEC/WSD. This simulator emulates an ERC32 system, containing the IU, FPU, MEC, up to 16 Mbyte ROM and up to 32 Mbyte RAM. Typical performance is 2 MIPS on a 400 MHz Pentium PC. Binaries for sunos-4.1.3, solaris-2.5, and Linux are available here.
Sis-3.0.1 includes the following new features:
- Correction of bugs in several IU and FPU instructions
- Correction of FPU trap handling
- Correction of timer and watchdog handling
- Accurate FPU timing (+- 2%)
- Accurate UART timing
- Simulation of watchdog clock
- Display MEC registers
- Memory and MEC registers writable from command line
- Dynamically configurable memory sizes (128K - 32M)
- Execute startup commands from .sisrc
- I/O area memory
ERC32 Cross Compilation System (ERC32CCS)
ERC32CCS-v2.0.1 - a GNU based cross-compiler system for ERC32
The erc32ccs is a cross-compilation system that consists of the following:
GNU C/C++ compiler (egcs-1.1.1) GNAT Ada 95 compiler (gnat-3.11p) Linker, assembler, archiver etc. (binutils-2.9.1) Standalone C-library (newlib-1.8.1 from Cygnus) RTEMS real-time kernel with ERC32 support (rtems-4.0.0) ERC32 boot-prom utility (mkprom-1.2.1) Standalone ERC32 simulator (sis-3.0.2) GNU debugger with ERC32 simulator (gdb-4.17 + sis-3.0.2) DDD graphical user interace for gdb (ddd-3.1.3) The erc32ccs allows cross-compilation of single or multi-treaded C, C++ and Ada95 applications for ERC32. Using the gdb debugger, it is possible to perform source-level symbolic debugging, either on the simulator or on a remote target. Binary versions for solaris-2.5, and linux-2.0 can be found here.If you have problems to download ftom the ESTEC ftp server, try this mirror.
The compilation system includes full documentation, you can browse individual documents before downloading.
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Last edited March 18, 1999
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