-------------------------------------------------------------------------------
STANDARDIZATION PROPOSAL:  (Strawman  Draft)
    	    	    	    Al Gilman, May 1989
     
DOMAIN:  Representation of Logic signals (interconnect) in VHDL.
Scope:  Standard declarations/names for inclusion in logic modeling
schemes.
     
-------------------------------------------------------------------------------
EXHIBIT:
The proposed standard is
"everything made visible by the following package declaration:"
     
use work.logic_private ;
package gen_logic is
     
subtype t_logic is logic_private.logic_states ;
     
  constant Unknown : t_logic ;
     
  constant Zero : t_logic ; -- low
  function Is_Zero ( In_Value : t_logic ) return BOOLEAN ;
     
  constant One : t_logic ; -- high
  function Is_One ( In_Value : t_logic ) return BOOLEAN ;
     
  constant High_Z : t_logic ; -- high impedance
  function Is_Z ( In_Value : t_logic ) return BOOLEAN ;
     
  constant Initial_state : t_logic ;
     
  function "=" (L,R: t_logic ) return BOOLEAN ;
  function "/=" (L,R: t_logic ) return BOOLEAN ;
  function "and" (L,R: t_logic ) return t_logic ;
  function "or" (L,R: t_logic ) return t_logic ;
  function "not" (R: t_logic ) return t_logic ;
  function "nand" (L,R: t_logic ) return t_logic ;
  function "nor" (L,R: t_logic ) return t_logic ;
  function "xor" (L,R: t_logic ) return t_logic ;
     
  type logic_vector is array (NATURAL range <>) of t_logic ;
     
  function and_vector ( In_Values : logic_vector ) return t_logic ;
  function or_vector ( In_Values : logic_vector ) return t_logic ;
  subtype wa_logic is and_vector t_logic ;
  subtype wo_logic is or_vector t_logic ;
  subtype wr_logic is logic_private.resolve t_logic ;
     
  function logic_to_bit ( In_Value : t_logic ) return bit ;
  function logic_to_bool ( In_Value : t_logic ) return boolean ;
  function bit_to_logic ( In_Value : bit ) return t_logic ;
  function bool_to_logic ( In_Value : boolean ) return t_logic ;
     
  type wa_vector is array (NATURAL range <>) of wa_logic ;
  type wo_vector is array (NATURAL range <>) of wo_logic ;
  type wr_vector is array (NATURAL range <>) of wr_logic ;
     
-- The following items exceed what is representable in four-state logic
     
  constant W_X : t_logic ; -- floating ambiguous
  constant W_Zero : t_logic ; -- floating low
  constant W_One : t_logic ; -- floating high
  constant R_X : t_logic ; -- resistive ambiguous
  constant R_Zero : t_logic ; -- resistive low
  constant R_One : t_logic ; -- resistive high
  constant S_X : t_logic ; -- driven/strong ambiguous
  constant S_Zero : t_logic ; -- driven/strong low
  constant S_One : t_logic ; -- driven/strong high
     
end gen_logic ;
     
-------------------------------------------------------------------------------
EXCLUSIONS:
Note that the standard is not "the full and exact text of this package."
In particular, the name "logic_private" of the package containing the underlying
type declaration IS NOT standardized by this standard, nor the logical name of
the library containing that package, nor the names of the intems in that
package USED herein.  It is solely the names exported from this package which
are the content of the standard.
     
Applications conforming to this abstract logic model shall use this package and
shall not use the package containing the underlying type declaration.
     
-------------------------------------------------------------------------------
SUBDIVISIONS:
     
If an application does not employ the constants (below the demarcation comment)
W_X, W_Zero, W_One, R_X, R_Zero, R_One, S_X, S_Zero, S_One, then it may be said
to conform to the [abstract] "four-state view" of this standard.  If any of
these names are used in constructing a model, it conforms to the "nine-state
view" instead.
     
-------------------------------------------------------------------------------
SEMANTICS:
     
It is not the intent to have unique semantics for these names.  In particular,
it is intended that this package may be implemented (the package body may
exist in alternative versions) somewhat differently for different technologies,
and to interface well to some incomplete VHDL implementations.
     
For example, in some technologies One is a strong one ( = S_One ) and in others
it is a resistive-strength value ( = R_One ).
     
However, the following example implementation demonstrates the intended
general meaning of these names.
     
package logic_private is
     
  type States is ( 'X', '0', '1' );
  type Strengths is ( 'W', 'R', 'S' );
     
     
  type logic_states is
        record
          State : States ;
          Strength : Strengths ;
        end record ;
     
  type logic_vector is array ( NATURAL range <> ) of logic_states ;
     
  function resolve ( in_array : in logic_vector ) return logic_states ;
     
end logic_private ;
     
package body logic_private is
     
  function resolve ( In_Array : in logic_vector ) return logic_states
    is
     
    variable Result : logic_states ;
    variable multiple_flag : BOOLEAN := False ;
     
    begin
     
      for I in In_Array'RANGE loop
     
        If I = In_Array'LOW then Result := In_Array(I) ;
        elsif In_Array(I).Strength > Result.Strength then
                Result := In_Array(I) ;
                multiple_flag := False ;
        elsif In_Array(I).Strength = Result.Strength then
                multiple_flag := True ;
                if In_Array(I).State /= Result.State then
                    Result.State := 'X' ;
                end if ;
        end if ;
     
      end loop ;
     
    assert not (multiple_flag and (Result.Strength = 'S'))
        report "Driver Collision"
        severity WARNING ;
     
    return Result ;
     
  end resolve ;
     
end logic_private ;
     
     
use work.logic_private.all ;
package body gen_logic is
     
  constant Unknown : t_logic := ('X','S') ;
     
  constant Zero : t_logic := ('0','S') ;
  function Is_Zero ( In_Value : t_logic ) return BOOLEAN
        is begin return In_Value.State = '0' ; end ;
     
  constant One : t_logic := ('1','S') ;
  function Is_One ( In_Value : t_logic ) return BOOLEAN
        is begin return In_Value.State = '1' ; end ;
     
  constant High_Z : t_logic := ('X','W') ;
  function Is_Z ( In_Value : t_logic ) return BOOLEAN
        is begin return In_Value.Strength = 'W' ; end ;
     
  constant Initial_state : t_logic := ('X','S') ;
     
  function "=" (L,R: t_logic ) return BOOLEAN
        is begin
        return work.logic_private."="(L,R) ; end ;
     
  function "/=" (L,R: t_logic ) return BOOLEAN
        is begin
        return work.logic_private."/="(L,R) ; end ;
     
  function "and" (L,R: t_logic ) return t_logic is
     
    variable result_state : States ;
    variable result_strength : Strengths ;
     
    begin
        if L.Strength > R.Strength then result_strength := L.Strength ;
        else result_strength := R.Strength ;
        end if ;
        if Is_Zero(L) or Is_Zero(R) then result_state := '0' ;
        elsif Is_One(L) and Is_One(R) then result_state := '1' ;
        else result_state := 'X' ;
        end if ;
        return (result_state, result_strength) ;
  end ;
     
  function "or" (L,R: t_logic ) return t_logic is
     
    variable result_state : States ;
    variable result_strength : Strengths ;
     
    begin
        if L.Strength > R.Strength then result_strength := L.Strength ;
        else result_strength := R.Strength ;
        end if ;
        if Is_One(L) or Is_One(R) then result_state := '1' ;
        elsif Is_Zero(L) and Is_Zero(R) then result_state := '0' ;
        else result_state := 'X' ;
        end if ;
        return (result_state, result_strength) ;
  end ;
     
  function "not" (R: t_logic ) return t_logic is
    begin
        If R.State = '1' then return ('0',R.Strength) ;
        elsif R.State = '0' then return ('1',R.Strength) ;
        else return R ;
        end if ;
  end ;
     
  function "nand" (L,R: t_logic ) return t_logic is
     
    variable result_state : States ;
    variable result_strength : Strengths ;
     
    begin
        if L.Strength > R.Strength then result_strength := L.Strength ;
        else result_strength := R.Strength ;
        end if ;
        if Is_Zero(L) or Is_Zero(R) then result_state := '1' ;
        elsif Is_One(L) and Is_One(R) then result_state := '0' ;
        else result_state := 'X' ;
        end if ;
        return (result_state, result_strength) ;
  end ;
     
  function "nor" (L,R: t_logic ) return t_logic is
     
    variable result_state : States ;
    variable result_strength : Strengths ;
     
    begin
        if L.Strength > R.Strength then result_strength := L.Strength ;
        else result_strength := R.Strength ;
        end if ;
        if Is_One(L) or Is_One(R) then result_state := '0' ;
        elsif Is_Zero(L) and Is_Zero(R) then result_state := '1' ;
        else result_state := 'X' ;
        end if ;
        return (result_state, result_strength) ;
  end ;
     
  function "xor" (L,R: t_logic ) return t_logic is
     
    variable result_state : States ;
    variable result_strength : Strengths ;
     
  begin
        if L.Strength > R.Strength then result_strength := L.Strength ;
            else result_strength := R.Strength ;
        end if ;
     
        if Is_One(L) and Is_One(R) then result_state := '0' ;
        elsif Is_Zero(L) and Is_Zero(R) then result_state := '0' ;
        elsif Is_Zero(L) and Is_One(R) then result_state := '1' ;
        elsif Is_One(L) and Is_Zero(R) then result_state := '1' ;
        else result_state := 'X' ;
        end if ;
     
        return (result_state, result_strength) ;
  end ;
     
  function and_vector ( In_Values : logic_vector ) return t_logic is
        variable Return_Value : t_logic := One ;
  begin
        for I in In_Values'RANGE loop
        Return_value := Return_Value and In_Values(I);
        end loop;
      return Return_Value ;
  end and_vector ;
     
  function or_vector ( In_Values : logic_vector ) return t_logic is
        variable Return_Value : t_logic := Zero ;
  begin
        for I in In_Values'RANGE loop
        Return_value := Return_Value or In_Values(I);
        end loop;
      return Return_Value ;
  end or_vector ;
     
  function logic_to_bit ( In_Value : t_logic ) return bit is
    begin
      if Is_One(In_Value) then return '1' ;
        else return '0' ;
      end if ;
  end logic_to_bit ;
     
function logic_to_bool ( In_Value : t_logic ) return boolean is
    begin
      if Is_One(In_Value) then return TRUE ;
        else return FALSE ;
      end if ;
  end logic_to_bool ;
     
  function bit_to_logic ( In_Value : bit ) return t_logic is
    begin
      case In_Value is
        when '0' =>
          return Zero ;
        when '1' =>
          return One ;
      end case;
  end bit_to_logic ;
     
  function bool_to_logic ( In_Value : boolean ) return t_logic is
    begin
      case In_Value is
        when FALSE =>
          return Zero ;
        when TRUE =>
          return One ;
      end case;
  end bool_to_logic ;
     
-- The following items exceed what is representable in four-state logic
     
  constant W_X : t_logic := ('X','W') ;
  constant W_Zero : t_logic := ('0','W') ;
  constant W_One : t_logic := ('1','W') ;
  constant R_X : t_logic := ('X','R') ;
  constant R_Zero : t_logic := ('0','R') ;
  constant R_One : t_logic := ('1','R') ;
  constant S_X : t_logic := ('X','S') ;
  constant S_Zero : t_logic := ('0','S') ;
  constant S_One : t_logic := ('1','S') ;
     
end gen_logic ;
     
--------------------------------------------------------------------------------

From gilman@inmet.inmet.com Fri Feb 24 16:50:20 1989
Received: by inmet.inmet.com (5.51/inmet.com)
	id AA29892; Fri, 24 Feb 89 16:51:53 EST
Date: Fri, 24 Feb 89 16:51:53 EST
From: gilman@inmet.inmet.com (Al Gilman)
Message-Id: <8902242151.AA29892@inmet.inmet.com>
To: gilman, jdegroat@BLACKBIRD
Status: R

(application of the abstract logic type (abstract logic-model interface) to
the construction of "layered" logic libraries)

----------------------------------------------------------------------------
library logic ;
use logic.gen_logic.all ;
package logic_utilities is
     
  signal Tied_Low : t_logic := Zero ;
  signal Tied_High : t_logic := One ;
  signal Tied_Off : t_logic := High_Z ;
     
  function "=" (L: t_logic; R: BIT) return BOOLEAN ;
  function "=" (L: BIT; R: t_logic) return BOOLEAN ;
  function "=" (L: t_logic; R: BOOLEAN) return BOOLEAN ;
  function "=" (L: BOOLEAN; R: t_logic) return BOOLEAN ;
     
  function "/=" (L: t_logic; R: BIT) return BOOLEAN ;
  function "/=" (L: BIT; R: t_logic) return BOOLEAN ;
  function "/=" (L: t_logic; R: BOOLEAN) return BOOLEAN ;
  function "/=" (L: BOOLEAN; R: t_logic) return BOOLEAN ;
     
  function "and" (L: t_logic; R: BIT) return BIT;
  function "and" (L: t_logic; R: BIT) return t_logic ;
  function "and" (L: BIT; R: t_logic) return BIT ;
  function "and" (L: BIT; R: t_logic) return t_logic ;
  function "and" (L: t_logic; R: BOOLEAN) return BOOLEAN ;
  function "and" (L: t_logic; R: BOOLEAN) return t_logic ;
  function "and" (L: BOOLEAN; R: t_logic) return BOOLEAN ;
  function "and" (L: BOOLEAN; R: t_logic) return t_logic ;
     
  function "or" (L: t_logic; R: BIT) return BIT;
  function "or" (L: t_logic; R: BIT) return t_logic ;
  function "or" (L: BIT; R: t_logic) return BIT ;
  function "or" (L: BIT; R: t_logic) return t_logic ;
  function "or" (L: t_logic; R: BOOLEAN) return BOOLEAN ;
  function "or" (L: t_logic; R: BOOLEAN) return t_logic ;
  function "or" (L: BOOLEAN; R: t_logic) return BOOLEAN ;
  function "or" (L: BOOLEAN; R: t_logic) return t_logic ;
     
  function "nor" (L: t_logic; R: BIT) return BIT;
  function "nor" (L: t_logic; R: BIT) return t_logic ;
  function "nor" (L: BIT; R: t_logic) return BIT ;
  function "nor" (L: BIT; R: t_logic) return t_logic ;
  function "nor" (L: t_logic; R: BOOLEAN) return BOOLEAN ;
  function "nor" (L: t_logic; R: BOOLEAN) return t_logic ;
  function "nor" (L: BOOLEAN; R: t_logic) return BOOLEAN ;
  function "nor" (L: BOOLEAN; R: t_logic) return t_logic ;
     
  function "nand" (L: t_logic; R: BIT) return BIT;
  function "nand" (L: t_logic; R: BIT) return t_logic ;
  function "nand" (L: BIT; R: t_logic) return BIT ;
  function "nand" (L: BIT; R: t_logic) return t_logic ;
  function "nand" (L: t_logic; R: BOOLEAN) return BOOLEAN ;
  function "nand" (L: t_logic; R: BOOLEAN) return t_logic ;
  function "nand" (L: BOOLEAN; R: t_logic) return BOOLEAN ;
  function "nand" (L: BOOLEAN; R: t_logic) return t_logic ;
     
  function "xor" (L: t_logic; R: BIT) return BIT;
  function "xor" (L: t_logic; R: BIT) return t_logic ;
  function "xor" (L: BIT; R: t_logic) return BIT ;
  function "xor" (L: BIT; R: t_logic) return t_logic ;
  function "xor" (L: t_logic; R: BOOLEAN) return BOOLEAN ;
  function "xor" (L: t_logic; R: BOOLEAN) return t_logic ;
  function "xor" (L: BOOLEAN; R: t_logic) return BOOLEAN ;
  function "xor" (L: BOOLEAN; R: t_logic) return t_logic ;
     
end logic_utilities ;
     
package body logic_utilities is
     
  function "=" (L: t_logic; R: BIT) return BOOLEAN
        is
        begin
        return logic_to_bit(L) = R ;
  end ;
     
  function "=" (L: BIT ; R: t_logic) return BOOLEAN
        is
        begin
        return L = logic_to_bit(R) ;
  end ;
     
  function "=" (L: t_logic; R: BOOLEAN) return BOOLEAN
        is
        begin
        return logic_to_bool(L) = R ;
  end ;
     
  function "=" (L: BOOLEAN ; R: t_logic) return BOOLEAN
        is
        begin
        return L = logic_to_bool(R) ;
  end ;
     
     
  function "/=" (L: t_logic; R: BIT) return BOOLEAN
        is
        begin
        return logic_to_bit(L) /= R ;
  end ;
     
  function "/=" (L: BIT ; R: t_logic) return BOOLEAN
        is
        begin
        return L /= logic_to_bit(R) ;
  end ;
     
  function "/=" (L: t_logic; R: BOOLEAN) return BOOLEAN
        is
        begin
        return logic_to_bool(L) /= R ;
  end ;
     
  function "/=" (L: BOOLEAN ; R: t_logic) return BOOLEAN
        is
        begin
        return L /= logic_to_bool(R) ;
  end ;
     
     
  function "and" (L: t_logic; R: BIT) return BIT
        is
        begin
        return logic_to_bit(L) and R ;
  end ;
     
  function "and" (L: t_logic; R: BIT) return t_logic
        is
        begin
        return L and bit_to_logic(R) ;
  end ;
     
  function "and" (L: BIT ; R: t_logic) return BIT
        is
        begin
        return L and logic_to_bit(R) ;
  end ;
     
  function "and" (L: BIT ; R: t_logic) return t_logic
        is
        begin
        return bit_to_logic(L) and R ;
  end ;
     
  function "and" (L: t_logic; R: BOOLEAN) return BOOLEAN
        is
        begin
        return logic_to_bool(L) and R ;
  end ;
     
  function "and" (L: t_logic; R: BOOLEAN) return t_logic
        is
        begin
        return L and bool_to_logic(R) ;
  end ;
     
  function "and" (L: BOOLEAN ; R: t_logic) return BOOLEAN
        is
        begin
        return L and logic_to_bool(R) ;
  end ;
     
  function "and" (L: BOOLEAN ; R: t_logic) return t_logic
        is
        begin
        return bool_to_logic(L) and R ;
  end ;
     
     
  function "or" (L: t_logic; R: BIT) return BIT
        is
        begin
        return logic_to_bit(L) or R ;
  end ;
     
  function "or" (L: t_logic; R: BIT) return t_logic
        is
        begin
        return L or bit_to_logic(R) ;
  end ;
     
  function "or" (L: BIT ; R: t_logic) return BIT
        is
        begin
        return L or logic_to_bit(R) ;
  end ;
     
  function "or" (L: BIT ; R: t_logic) return t_logic
        is
        begin
        return bit_to_logic(L) or R ;
  end ;
     
  function "or" (L: t_logic; R: BOOLEAN) return BOOLEAN
        is
        begin
        return logic_to_bool(L) or R ;
  end ;
     
  function "or" (L: t_logic; R: BOOLEAN) return t_logic
        is
        begin
        return L or bool_to_logic(R) ;
  end ;
     
  function "or" (L: BOOLEAN ; R: t_logic) return BOOLEAN
        is
        begin
        return L or logic_to_bool(R) ;
  end ;
     
  function "or" (L: BOOLEAN ; R: t_logic) return t_logic
        is
        begin
        return bool_to_logic(L) or R ;
  end ;
     
     
  function "nor" (L: t_logic; R: BIT) return BIT
        is
        begin
        return logic_to_bit(L) nor R ;
  end ;
     
  function "nor" (L: t_logic; R: BIT) return t_logic
        is
        begin
        return L nor bit_to_logic(R) ;
  end ;
     
  function "nor" (L: BIT ; R: t_logic) return BIT
        is
        begin
        return L nor logic_to_bit(R) ;
  end ;
     
  function "nor" (L: BIT ; R: t_logic) return t_logic
        is
        begin
        return bit_to_logic(L) nor R ;
  end ;
     
  function "nor" (L: t_logic; R: BOOLEAN) return BOOLEAN
        is
        begin
        return logic_to_bool(L) nor R ;
  end ;
     
  function "nor" (L: t_logic; R: BOOLEAN) return t_logic
        is
        begin
        return L nor bool_to_logic(R) ;
  end ;
     
  function "nor" (L: BOOLEAN ; R: t_logic) return BOOLEAN
        is
        begin
        return L nor logic_to_bool(R) ;
  end ;
     
  function "nor" (L: BOOLEAN ; R: t_logic) return t_logic
        is
        begin
        return bool_to_logic(L) nor R ;
  end ;
     
     
  function "nand" (L: t_logic; R: BIT) return BIT
        is
        begin
        return logic_to_bit(L) nand R ;
  end ;
     
  function "nand" (L: t_logic; R: BIT) return t_logic
        is
        begin
        return L nand bit_to_logic(R) ;
  end ;
     
  function "nand" (L: BIT ; R: t_logic) return BIT
        is
        begin
        return L nand logic_to_bit(R) ;
  end ;
     
  function "nand" (L: BIT ; R: t_logic) return t_logic
        is
        begin
        return bit_to_logic(L) nand R ;
  end ;
     
  function "nand" (L: t_logic; R: BOOLEAN) return BOOLEAN
        is
        begin
        return logic_to_bool(L) nand R ;
  end ;
     
  function "nand" (L: t_logic; R: BOOLEAN) return t_logic
        is
        begin
        return L nand bool_to_logic(R) ;
  end ;
     
  function "nand" (L: BOOLEAN ; R: t_logic) return BOOLEAN
        is
        begin
        return L nand logic_to_bool(R) ;
  end ;
     
  function "nand" (L: BOOLEAN ; R: t_logic) return t_logic
        is
        begin
        return bool_to_logic(L) nand R ;
  end ;
     
     
  function "xor" (L: t_logic; R: BIT) return BIT
        is
        begin
        return logic_to_bit(L) xor R ;
  end ;
     
  function "xor" (L: t_logic; R: BIT) return t_logic
        is
        begin
        return L xor bit_to_logic(R) ;
  end ;
     
  function "xor" (L: BIT ; R: t_logic) return BIT
        is
        begin
        return L xor logic_to_bit(R) ;
  end ;
     
  function "xor" (L: BIT ; R: t_logic) return t_logic
        is
        begin
        return bit_to_logic(L) xor R ;
  end ;
     
  function "xor" (L: t_logic; R: BOOLEAN) return BOOLEAN
        is
        begin
        return logic_to_bool(L) xor R ;
  end ;
     
  function "xor" (L: t_logic; R: BOOLEAN) return t_logic
        is
        begin
        return L xor bool_to_logic(R) ;
  end ;
     
  function "xor" (L: BOOLEAN ; R: t_logic) return BOOLEAN
        is
        begin
        return L xor logic_to_bool(R) ;
  end ;
     
  function "xor" (L: BOOLEAN ; R: t_logic) return t_logic
        is
        begin
        return bool_to_logic(L) xor R ;
  end ;
     
     
end logic_utilities ;
     
library logic;
use logic.gen_logic.all ;
entity AND_GATE is
  generic
  (tPLH : Time := 1ns ;
   tPHL : Time := 1ns ) ;
  port
  (INPUT_1  : in  t_logic := One ;
   INPUT_2  : in  t_logic := One ;
   INPUT_3  : in  t_logic := One ;
   INPUT_4  : in  t_logic := One ;
   OUTPUT : out t_logic := Zero) ;
     
end AND_GATE ;
     
architecture ARCH of AND_GATE is
begin
  process (INPUT_1, INPUT_2, INPUT_3, INPUT_4)
    variable Result : t_logic := One ;
    variable delay  : Time  := tPLH ;
  begin
    Result := and_vector ((INPUT_1, INPUT_2, INPUT_3, INPUT_4)) ;
     
    if Is_Zero(Result) then delay := tPHL ;
    elsif Is_One(Result) then delay := tPLH ;
    else delay := 0 ns ;
    end if ;
     
    OUTPUT <= Result after delay ;
  end process ;
end ARCH ;
     
-------------------------------------------------------------------------------
library logic;
use logic.gen_logic.all ;
entity BUF is
  generic
  (tPLH : Time := 1ns ;
   tPHL : Time := 1ns) ;
  port
  (INPUT  :  in t_logic := Zero ;
   OUTPUT :  out t_logic := Zero) ;
end BUF ;
     
architecture ARCH of BUF is
begin
  process (INPUT)
    variable result : t_logic := Zero ;
  begin
    result := INPUT ;
    if Is_Z(INPUT) then result := Unknown ;
    end if ;
    if Is_One(INPUT) then
      OUTPUT <= result after tPLH ;
    elsif Is_Zero(INPUT) then
      OUTPUT <= result after tPHL ;
    else
      OUTPUT <= result ;
    end if ;
  end process ;
end ARCH ;
-------------------------------------------------------------------------
library logic;
use logic.gen_logic.all ;
entity DFF is
  generic
  (tPLH, tPHL : Time := 1ns ;
   tPCL, tPPH : Time := 1ns) ;
  port
  (D, CLK : in t_logic := Zero ;
   NOT_PRESET, NOT_CLEAR : in t_logic := One ;
   Q, QB : out t_logic := Zero) ;
end DFF ;
     
architecture ARCH of DFF is
        signal result : t_logic := Zero ;
        signal delay : TIME := 1 ns ;
begin
synchronous_behavior:
  process (CLK)
  begin
    if Is_One(CLK) then
      if Is_One(D) then
        result <= One ;
        delay <= tPLH ;
      else
        result <= Zero ;
        delay <= tPHL ;
      end if ;
    end if ;
  end process ;
     
asynchronous_behavior:
  process (NOT_PRESET, NOT_CLEAR, result)
  begin
    assert not (Is_Zero(NOT_PRESET) and Is_Zero(NOT_CLEAR))
      report "PRESET and CLEAR both active on D-Flip-Flop"
      severity Warning ;
     
    if Is_Zero(NOT_PRESET) and Is_One(NOT_CLEAR) then
        Q <= One after tPPH ; QB <= Zero after tPPH ;
    elsif Is_One(NOT_PRESET) and Is_Zero(NOT_CLEAR) then
        Q <= Zero after tPCL ; QB <= One after tPCL ;
    else
        Q <= result after delay;
        if Is_Zero(result) then QB <= One after delay;
        elsif Is_One(result) then QB <= Zero after delay;
        else QB <= Unknown ;
        end if ;
    end if ;
  end process ;
end ARCH ;
-------------------------------------------------------------------------
library logic;
use logic.gen_logic.all ;
entity INVERTER is
  generic
  (tPLH : Time := 1ns ;
   tPHL : Time := 1ns) ;
  port
  (INPUT : in t_logic := Zero ;
   OUTPUT  : out t_logic := Zero) ;
end INVERTER ;
     
architecture ARCH of INVERTER is
begin
  process (INPUT)
    variable result : t_logic := Zero ;
    variable delay  : Time  := 1ns ;
  begin
    if Is_Zero(INPUT) then
      Result := One ;
      Delay := tPLH ;
    elsif Is_One(INPUT) then
      Result := Zero ;
      Delay := tPHL ;
    else
      Result := Unknown ;
    end if ;
    OUTPUT <= Result after Delay ;
  end process ;
end ARCH ;
-------------------------------------------------------------------------
     
library logic;
use logic.gen_logic.all ;
entity NAND_GATE is
  generic
  (tPLH : Time := 0ns ;
   tPHL : Time := 0ns) ;
  port
  (INPUT_1  : in  t_logic := One ;
   INPUT_2  : in  t_logic := One ;
   INPUT_3  : in  t_logic := One ;
   INPUT_4  : in  t_logic := One ;
   OUTPUT : out t_logic := Zero) ;
end NAND_GATE ;
     
architecture ARCH of NAND_GATE is
begin
  process (INPUT_1, INPUT_2, INPUT_3, INPUT_4)
    variable Result : t_logic := One ;
    variable delay  : Time  := tPLH ;
  begin
    Result := not and_vector ((INPUT_1, INPUT_2, INPUT_3, INPUT_4)) ;
     
    if Is_Zero(result) then delay := tPHL ;
    elsif Is_One(result) then delay := tPLH ;
    else delay := 0 ns ;
    end if ;
     
    OUTPUT <= Result after delay ;
  end process ;
end ARCH ;
-------------------------------------------------------------------------
library logic;
use logic.gen_logic.all ;
entity NOR_GATE is
  generic
  (tPLH : Time := 0ns ;
   tPHL : Time := 0ns) ;
  port
  (INPUT_1  : in t_logic := Zero ;
   INPUT_2  : in t_logic := Zero ;
   INPUT_3  : in t_logic := Zero ;
   INPUT_4  : in t_logic := Zero ;
   OUTPUT : out t_logic := Zero) ;
end NOR_GATE ;
     
architecture ARCH of NOR_GATE is
begin
  process ( INPUT_1, INPUT_2,INPUT_3,INPUT_4 )
    variable Result : t_logic := One ;
    variable delay  : Time  := tPLH ;
  begin
    Result := not or_vector (( INPUT_1, INPUT_2,INPUT_3,INPUT_4 ));
     
    if Is_Zero(result) then delay := tPHL ;
    elsif Is_One(result) then delay := tPLH ;
    else delay := 0 ns ;
    end if ;
     
    OUTPUT <= Result after delay ;
  end process ;
end ARCH ;
-------------------------------------------------------------------------
library logic;
use logic.gen_logic.all ;
entity OR_GATE is
  generic
  (tPLH : Time := 0ns ;
   tPHL : Time := 0ns) ;
  port
  (INPUT_1  : in t_logic := Zero ;
   INPUT_2  : in t_logic := Zero ;
   INPUT_3  : in t_logic := Zero ;
   INPUT_4  : in t_logic := Zero ;
   OUTPUT : out t_logic := Zero) ;
end OR_GATE ;
     
architecture ARCH of OR_GATE is
begin
  process ( INPUT_1, INPUT_2,INPUT_3,INPUT_4 )
    variable Result : t_logic := One ;
    variable delay  : Time  := tPLH ;
  begin
    Result := or_vector (( INPUT_1, INPUT_2,INPUT_3,INPUT_4 ));
     
    if Is_Zero(result) then delay := tPHL ;
    elsif Is_One(result) then delay := tPLH ;
    else delay := 0 ns ;
    end if ;
     
    OUTPUT <= Result after delay ;
  end process ;
end ARCH ;
-------------------------------------------------------------------------
     
library logic;
use logic.gen_logic.all ;
entity XOR_GATE is
  generic
  (tPLH : Time := 1ns ;
   tPHL : Time := 1ns) ;
  port
  (INPUT_1, INPUT_2 : in  t_logic ;
   OUTPUT : out t_logic := Initial_State ) ;
end XOR_GATE ;
     
architecture ARCH of XOR_GATE is
begin
  process (INPUT_1, INPUT_2)
  variable result : t_logic ;
  begin
    result := INPUT_1 xor INPUT_2 ;
    if Is_One(Result) then OUTPUT <= result after tPLH ;
    elsif Is_Zero(Result) then OUTPUT <= result after tPHL ;
    else OUTPUT <= Unknown ;
    end if ;
  end process ;
     
end ARCH ;
     
library logic;
use logic.gen_logic.all;
entity ZINVERTER is
  generic
  (tPLH, tPHL : Time := 0ns ;
   tPLZ, tPHZ : Time := 0ns ;
   tPZL, tPZH : Time := 0ns) ;
  port
  (ENB    : in    t_logic := Zero ;
   INPUT  : in    t_logic := Unknown ;
   OUTPUT : out t_logic := High_Z) ;
end ZINVERTER ;
     
architecture ARCH of ZINVERTER is
begin
  process (INPUT, ENB)
    variable result,old_result : t_logic := High_Z ;
    variable delay  : Time  := 0ns ;
  begin
    if Is_One(ENB) then
      result := High_Z ;
        if Is_Zero(old_result) then result := High_Z ; delay := tPLZ ;
        elsif Is_One(old_result) then result := High_Z ; delay := tPHZ ;
        end if;
    elsif Is_Zero(ENB) then
      if Is_Zero(INPUT) then
        result := One ;
      elsif Is_One(INPUT) then
        result := Zero ;
      else
        result := Unknown ;
      end if ;
      if Is_One(result) then
        if Is_Z(old_result) then delay := tPZH ;
        elsif Is_Zero(old_result) then delay := tPLH ;
        end if ;
      elsif Is_Zero(result) then
        if Is_Z(old_result) then delay := tPZL ;
        elsif Is_One(old_result) then delay := tPHL ;
        end if ;
      end if ;
     
    else Result := Unknown ;
     
    end if ;
     
    OUTPUT <= Result after Delay ;
    old_result := result ;
     
  end process ;
end ARCH ;
     

From gilman@inmet.inmet.com Fri Feb 24 16:51:26 1989
Received: by inmet.inmet.com (5.51/inmet.com)
	id AA29913; Fri, 24 Feb 89 16:53:15 EST
Date: Fri, 24 Feb 89 16:53:15 EST
From: gilman@inmet.inmet.com (Al Gilman)
Message-Id: <8902242153.AA29913@inmet.inmet.com>
To: jdegroat@BLACKBIRD
Status: R

(a simulatable circuit-description using the abstract interface to its logic
model.)

--------------------------------------------------------------------------------

library logic;
use logic.gen_logic.all;
entity HEX_COUNT is
port (
        Carry_In : in t_logic ;
        CLK : in t_logic ;
        NOT_CLEAR : in t_logic := One ;
        NOT_PRESET : in t_logic := One ;
        Bit_0 : inout t_logic ;
        Bit_1 : inout t_logic ;
        Bit_2 : inout t_logic ;
        Bit_3 : inout t_logic ;
        Carry_Out : inout t_logic
     ) ;
end HEX_COUNT ;
     
architecture ARCH of HEX_COUNT is
     
        component  AND_GATE
          port    (INPUT_1  : in  t_logic ;
                   INPUT_2  : in  t_logic ;
                   OUTPUT : out t_logic ) ;
        end component ;
     
        for all: AND_GATE use entity logic.AND_GATE(ARCH) ;
     
        component  DFF
          port    (D, CLK : in t_logic  ;
                   NOT_PRESET, NOT_CLEAR : in t_logic  ;
                   Q , QB : out t_logic ) ;
        end component ;
     
        for all: DFF use entity logic.DFF(ARCH) ;
     
        component  XOR_GATE
          port    (INPUT_1  : in t_logic ;
                   INPUT_2  : in t_logic ;
                   OUTPUT : out t_logic ) ;
        end component ;
     
        for all: XOR_GATE use entity logic.XOR_GATE(ARCH) ;
     
        signal Save_0, Save_1, Save_2, Save_3 : t_logic := Zero;
        signal Carry_0, Carry_1, Carry_2 : t_logic := Zero;
     
BEGIN
     
-- Stage 0 -----
     
        And_0: AND_GATE port map (INPUT_1  => Carry_In,
                                  INPUT_2  => Bit_0,
                                  OUTPUT => Carry_0);
     
        Xor_0: XOR_GATE port map (INPUT_1  => Carry_In,
                                  INPUT_2  => Bit_0,
                                  OUTPUT => Save_0);
     
        DFF_0: DFF      port map (CLK   => CLK,
                                  D     => Save_0,
                                  Q     => Bit_0 ,
                                  NOT_CLEAR => NOT_CLEAR ,
                                  NOT_PRESET => NOT_PRESET );
-- Stage 1 -----
     
        And_1: AND_GATE port map (INPUT_1  => Carry_0,
                                  INPUT_2  => Bit_1,
                                  OUTPUT => Carry_1);
     
        Xor_1: XOR_GATE port map (INPUT_1  => Carry_0,
                                  INPUT_2  => Bit_1,
                                  OUTPUT => Save_1);
     
        DFF_1: DFF      port map (CLK   => CLK,
                                  D     => Save_1,
                                  Q     => Bit_1,
                                  NOT_CLEAR => NOT_CLEAR ,
                                  NOT_PRESET => NOT_PRESET );
     
-- Stage 2 -----
     
        And_2: AND_GATE port map (INPUT_1  => Carry_1,
                                  INPUT_2  => Bit_2,
                                  OUTPUT => Carry_2);
     
        Xor_2: XOR_GATE port map (INPUT_1  => Carry_1,
                                  INPUT_2  => Bit_2,
                                  OUTPUT => Save_2);
     
        DFF_2: DFF      port map (CLK   => CLK,
                                  D     => Save_2,
                                  Q     => Bit_2 ,
                                  NOT_CLEAR => NOT_CLEAR ,
                                  NOT_PRESET => NOT_PRESET );
     
-- Stage 3 -----
     
        And_3: AND_GATE port map (INPUT_1  => Carry_2,
                                  INPUT_2  => Bit_3,
                                  OUTPUT => Carry_Out);
     
        Xor_3: XOR_GATE port map (INPUT_1  => Carry_2,
                                  INPUT_2  => Bit_3,
                                  OUTPUT => Save_3);
     
        DFF_3: DFF      port map (CLK   => CLK,
                                  D     => Save_3,
                                  Q     => Bit_3,
                                  NOT_CLEAR => NOT_CLEAR ,
                                  NOT_PRESET => NOT_PRESET );
     
end ARCH ;
     
entity test_counter is end;
     
----------------------------------------------
-- TEST BENCH CONTAINING COUNTER CIRCUIT
----------------------------------------------
     
library logic;
use logic.gen_logic.all;
architecture HEX of TEST_COUNTER is
     
        signal CLK : t_logic := Zero;
        signal Carry_Out, Not_Clear : t_logic := Zero ;
        signal Tied_Low : t_logic := Zero ;
        signal Tied_High : t_logic := One ;
        signal Bits : logic_vector(0 to 3) := (others => Zero) ;
        signal count : INTEGER := 0 ;
     
        component COUNTER
        port (
        Carry_In : in t_logic ;
        CLK : in t_logic ;
        NOT_CLEAR : in t_logic := One ;
        NOT_PRESET : in t_logic := One ;
        Bit_0 : inout t_logic ;
        Bit_1 : inout t_logic ;
        Bit_2 : inout t_logic ;
        Bit_3 : inout t_logic ;
        Carry_Out : inout t_logic
             ) ;
        end COMPONENT ;
     
        for all : COUNTER use entity work.HEX_COUNT(ARCH) ;
     
BEGIN
     
System_Clock: CLK <= not CLK after 5 ns ;
     
        count <= count + 1 after 10 ns ;
     
abnormal_ending:
        assert count < 31 report " sim overrun " severity error;
     
normal_ending: process ( CLK )
                begin
                assert not (Is_One(CLK) and Is_One(Carry_Out))
                report " count wrapped -- OK -- sim done "
                severity error ;
        end process ;
     
power_up: Not_Clear <= Zero, One after 2 ns ;
     
UUT:    COUNTER
        port MAP
        (
        Carry_In => Tied_High ,
        CLK => CLK ,
        NOT_CLEAR => Not_Clear ,
        NOT_PRESET => Tied_High ,
        Bit_0 => Bits(0) ,
        Bit_1 => Bits(1) ,
        Bit_2 => Bits(2) ,
        Bit_3 => Bits(3) ,
        Carry_Out => Carry_Out
        )
        ;
     
end HEX ;