DLX Single Cycle Memory Interface

DLX Single Cycle Memory Interface: Due Feb 13 at Class Time

Introduction

In this lab we will modify the single cycle implementation to be able to handle byte and half-word load/stores correctly. This involves creating a load alignment/extension block and store alignment block as discussed in class.

Set Up

Copy the file '~reese/vhdl.tar.Z.sim2' from my ECE acccount to your local directory. Unpack this compressed tar file by doing:


   % cat vhdl.tar.Z.sim2 | zcat | tar xf -

This will create the directory development tree like the one you used for the first VHDL simulation assignment( You will need to delete the directory tree you used in the first assignment). For PC users, the file you need is called 'sim2.zip'.

What You Have To Do

You will need to modify the 'load_align.vhd' and 'store_align.vhd' models so that load and store alignment is performed correctly as discussed in class. Use the VHDL configuration 'cfg_mem_test' during simulation:


 qhsim -lib ../obj/qhdl/dlxsimple cfg_mem_test

This loads the 'mem_test.obj' file which was produced from 'mem_test.s' The correct register values at the end of the simulation are specified in 'mem_test.s'.

Tips

You will find it useful to be able to assign a bit range of one bus to a bit range in another bus. The assignment below:


 dout <= din;   -- din, dout are 32-bit busses

assigns all of the bits of bus din to dout. The following assignments:


 dout(31 downto 16)  <= din(15 downto 0);  -- lower 16 bits of din to din

 dout(7 downto 0)  <= din(31 downto 24);  -- upper byte to lower byte

 dout(23 downto 16) <= "00000000";        -- assign to zero

show examples of partial range assignments. You may also need to write 'if - then -elsif' statements. The format for these are:


  if (condition) then
    statement a
    statement b
    ...
  elsif  (condition)  then
    statement a
    statement b
    ...
  elsif  (condition)  then
    statement a
    statement b
    ...

  end if;

Note that 'elsif' is all one word and the 'elsif' is missing the 'e' in the 'else'. You only need one 'end if' to end the statement.

To Turn In

Email your modified 'load_align.vhd' and 'store_align.vhd' to me. Also, in your mail message, give me the STATUS of your simulation. State whether or not you are able to match the correct register values; if not, give the register names and values which DO NOT match. If you supply incorrect status information (i.e. state that your simulation is working when it is not) then your grade will be penalized very heavily.