MPL VHDL Model Collection

Getting Started

Here are the quick steps needed to simulate a Xilinx x4000 design.

1. Down load the x4000 vhdl library
2. Compile the library following the CompilationOrder file in the model library
3. Use the LCA Upload -> VHDL Model Generation/Download to submit your LCA file for conversion into a vhdl structural model. Note: You must have Netscape 2.0 to perform this step.
4. Compile the downloaded vhdl structural model and simulate

Send Questions/Comments to mpl-vhdl@ERC.MsState.Edu

New Release!!
There is a new release of the Xilinx Library. You must download it to use with the latest release of lca2vhd.

All guests must register to download Xilinx X4000 library from the MPL VHDL Model Collection. Please enter your email address below.

last updated 03-19-97 Version 2.1