echo x - s-04-3-3-0008a.vhdl
sed 's/^X//' >s-04-3-3-0008a.vhdl <<'*-*-END-of-s-04-3-3-0008a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X	--
X	--		Copyright Intermetrics 1986
X	--
X	-- 	This material may be reproduced by or for the 
X	--      U.S. Government pursuant to the copyright license 
X	-- 	under DAR clause 7-104.9(a) (1981 May)
X	--
X	--
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-04-2-2-0008A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid:  -- %G% %W% --
X-- Description:
X-- Check that multiple signal assignment statements and association lists
X-- are permitted for updating interface elements of type signal and modes
X-- "out" or "inout".
X-- 
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)Ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xpackage bus_defs is
X
X    type bus_int is range 0 to INTEGER'HIGH;
X    type unconst is array(integer range <>) of bus_int;    
X    function resolve (sigs : unconst) return bus_int;
X    subtype Ibus is atomic resolve bus_int;
Xend bus_defs;
X
Xpackage body bus_defs is
X    function resolve (sigs : unconst) return bus_int is
X      begin
X	return 1;
X    end resolve;
Xend bus_defs;	
X
X-- with package bus_defs; 
Xuse bus_defs.all;
Xentity E  is
X    port ( V1:  out   Ibus;
X	   V2 : inout Ibus;
X	   V3 : out   Ibus;
X	   V4 : inout Ibus
X	 ) ;
Xend E;
X
Xarchitecture AB of E is
X-- L_X_1: block
X  
X signal L1 : bus_int; 
X signal L2 : bus_int; 
X signal L3 : bus_int ; 
X signal L4 : bus_int ; 
X
X
X component C1 port (  S1: out   Ibus ;
X                      S2: inout Ibus ;
X                      S3: out   Ibus ;
X                      S4: inout Ibus);
X begin
X  CIS1 : C1 port (S1 => V1, S2 => V2, S3 => V3, S4 => V4);
X  CIS2 : C1 port ( V1, V2, V3, V4);
X  process
X     begin
X       V1 <= L1;
X       V2 <= L2;
X       V3 <= L3;
X       V4 <= L4;
X  end process;
X--  end block;
Xend AB;
X   
*-*-END-of-s-04-3-3-0008a.vhdl-*-*
echo x - s-04-3-3-0009a.vhdl
sed 's/^X//' >s-04-3-3-0009a.vhdl <<'*-*-END-of-s-04-3-3-0009a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X	--
X	--		Copyright Intermetrics 1986
X	--
X	-- 	This material may be reproduced by or for the 
X	--      U.S. Government pursuant to the copyright license 
X	-- 	under DAR clause 7-104.9(a) (1981 May)
X	--
X	--
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-04-2-2-0009A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid:  -- %G% %W% --
X-- Description:
X-- Check that updating of interface elements of mode "buffer" is permitted.
X-- 
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)Ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E  is 
X    port ( P1 : buffer BIT) ;
Xend E;
X
Xarchitecture AB of E is
X-- L_X_1: block
X 
X-- CRJ    component C1 port (S1 : buffer Bit);
X-- CRJ    port map ( S1 => P1)
X  
X begin
X  process
X  begin
X    
X    P1 <= transport '1';
X  end process;
X--  end block;
Xend AB;
*-*-END-of-s-04-3-3-0009a.vhdl-*-*
echo x - s-04-3-3-0010a.vhdl
sed 's/^X//' >s-04-3-3-0010a.vhdl <<'*-*-END-of-s-04-3-3-0010a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X	--
X	--		Copyright Intermetrics 1986
X	--
X	-- 	This material may be reproduced by or for the 
X	--      U.S. Government pursuant to the copyright license 
X	-- 	under DAR clause 7-104.9(a) (1981 May)
X	--
X	--
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-04-2-2-0010A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid:  -- %G% %W% --
X-- Description:
X-- Check that reading and updating of interface elements of mode "linkage"
X-- is permitted for actual signals corresponding to interface elements of 
X-- mode "linkage".
X-- 
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)Ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
X
Xentity EC  is
X    port (A : linkage Bit) ;
Xend EC;
X
Xarchitecture AB of EC is
X-- L_X_1: block
X
X    component Local port (CL : linkage  Bit);
X
X begin
X     CIS1 : Local port (CL => A); 
X--  end block;
Xend AB;
X
*-*-END-of-s-04-3-3-0010a.vhdl-*-*
echo x - s-04-3-3-0011a.vhdl
sed 's/^X//' >s-04-3-3-0011a.vhdl <<'*-*-END-of-s-04-3-3-0011a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X	--
X	--		Copyright Intermetrics 1986
X	--
X	-- 	This material may be reproduced by or for the 
X	--      U.S. Government pursuant to the copyright license 
X	-- 	under DAR clause 7-104.9(a) (1981 May)
X	--
X	--
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-04-2-2-0011A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid:  -- %G% %W% --
X-- Description:
X-- Check that default expressions are optional for interface elements of mode
X-- "in" in subprograms parameter interface list, formal generic lists, and
X-- formal part lists.
X-- 
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)Ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E  is
Xgeneric ( A : integer := 5 ) ;
X    port (PT : BOOLEAN := true) ;
Xend E;
X
Xentity E1  is
Xgeneric ( A : integer ) ;
X    port (LT : BOOLEAN) ;
Xend E1;
X
X
X
Xpackage P is
Xfunction F ( BAD : integer := 0) return boolean;
Xfunction F2 ( BAD : integer ) return boolean;
Xend P;
X
Xpackage body P is
X
Xfunction F ( BAD : integer := 0) return boolean is
X begin
X  return true;
Xend F;
X 
Xfunction F2 ( BAD : integer ) return boolean is
X begin
X  return true;
Xend F2;
Xend P;
X
Xentity E3 is
X
Xend E3;
X
Xentity E4 is
X
Xend E4;
*-*-END-of-s-04-3-3-0011a.vhdl-*-*
echo x - s-04-3-4-0001a.vhdl
sed 's/^X//' >s-04-3-4-0001a.vhdl <<'*-*-END-of-s-04-3-4-0001a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X	--
X	--		Copyright Intermetrics 1986
X	--
X	-- 	This material may be reproduced by or for the 
X	--      U.S. Government pursuant to the copyright license 
X	-- 	under DAR clause 7-104.9(a) (1981 May)
X	--
X	--
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-04-2-1-4001A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid:  -- %G% %W% --
X-- Description:
X-- Check that the identifier specified in an alias declaration denotes
X-- the alias name everywhere both are visible.
X-- 
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)Ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
X entity E  is
X     port (PT: BOOLEAN) ;
X    constant C1 : BOOLEAN := TRUE;
X    alias FAKE : BOOLEAN is C1;
X end E;
X
Xarchitecture BB of E is
X-- B: block
X begin
X  process
X   constant CX : BOOLEAN := FAKE;
X  
X  begin
X    IF FAKE  then
X       return;
X    end if;
X  end process;
X--  end block; 
Xend BB;
*-*-END-of-s-04-3-4-0001a.vhdl-*-*
echo x - s-04-3-4-0002a.vhdl
sed 's/^X//' >s-04-3-4-0002a.vhdl <<'*-*-END-of-s-04-3-4-0002a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X	--
X	--		Copyright Intermetrics 1986
X	--
X	-- 	This material may be reproduced by or for the 
X	--      U.S. Government pursuant to the copyright license 
X	-- 	under DAR clause 7-104.9(a) (1981 May)
X	--
X	--
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-04-2-1-4002A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid:  -- %G% %W% --
X-- Description:
X--    Check that the name in an alias declaration may denote a constant,
X--    a variable, a signal, a formal port, a formal generic, a formal
X--    subprogram parameter, or an element or slice of another object.
X-- 
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)Ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xpackage t1 is
X
X   type rec is record
X	a : integer;
X    end record;
X
X   constant SL : severity_level := Note;
X   alias SL_too : severity_level is SL;   -- constant alias
X
X   procedure proc (k : inout severity_level);
Xend t1;
X
Xpackage body t1 is
X   procedure proc (k : inout severity_level) is
X	alias K_too : severity_level is k; -- formal subprogram parm alias
X
X   	variable VV : Boolean;
X        alias VV_too : boolean is VV; -- Variable alias
X
X	variable R1 : rec;
X	alias Fake : integer is R1.a;
X                      -- Composite Object Element alias	
X     begin
X        VV := TRUE;
X	if K_too = SL_too then
X          return ;
X        end if;
X   end proc;
Xend t1;
X
Xentity YU           is
X	   generic (GEN : BOOLEAN) ;
X	       port (PT  : inout BIT ) ;
X
X
X  alias PT_TOO  : BIT is PT;  -- formal port alias
X  alias GEN_TOO : boolean is GEN;  -- formal generic alias
Xend YU;
X
Xarchitecture WU of YU is
X-- HH: block
X	signal SSS : BIT;
X  	alias SSS_too : BIT is SSS;  -- Signal alias
X        signal REAL_NUMBER : BIT_VECTOR( 0 to 31);
X
X        type arr is array ( 1 to 8) of integer;
X	signal Sar : arr;
X	alias SAR1_too : integer is Sar(1); -- Composite object element alias
X        alias EXPONENT : BIT_VECTOR( 1 to 7) is REAL_NUMBER( 1 to 7);
X                                            -- slice alias of another object
X    begin
X	PT_TOO <= SSS_too; 
X--     end block;
Xend WU;
*-*-END-of-s-04-3-4-0002a.vhdl-*-*
echo x - s-04-3-4-0003a.vhdl
sed 's/^X//' >s-04-3-4-0003a.vhdl <<'*-*-END-of-s-04-3-4-0003a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X	--
X	--		Copyright Intermetrics 1986
X	--
X	-- 	This material may be reproduced by or for the 
X	--      U.S. Government pursuant to the copyright license 
X	-- 	under DAR clause 7-104.9(a) (1981 May)
X	--
X	--
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-04-2-1-4003A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid:  -- %G% %W% --
X-- Description:
X--   Check that the subtype indication in an alias declaration may specify
X--   a different direction from that specified in the declaration of the
X--   object it denotes.
X-- 
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)Ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xpackage Three_a is
X	type meters is (one_hr, two_hr, nine_hr);
X	
X        function N return boolean;
Xend Three_a;
X
Xpackage body Three_a is
X        function N return boolean is
X	    variable early_choice : meters range nine_hr downto one_hr;
X		-- Object has descending direction.
X	    alias late_choice : meters range one_hr to nine_hr is early_choice;
X  		-- Alias has ascending direction.
X      	  begin
X		return True;
X	end N;
Xend Three_a;			
*-*-END-of-s-04-3-4-0003a.vhdl-*-*
echo x - s-04-4-0-0001a.vhdl
sed 's/^X//' >s-04-4-0-0001a.vhdl <<'*-*-END-of-s-04-4-0-0001a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X	--
X	--		Copyright Intermetrics 1986
X	--
X	-- 	This material may be reproduced by or for the 
X	--      U.S. Government pursuant to the copyright license 
X	-- 	under DAR clause 7-104.9(a) (1981 May)
X	--
X	--
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-04-3-2-0001A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid:  -- %G% %W% --
X-- Description:
X-- Check that an item inherits an attribute if the declaration of the entity
X-- is accompanied by an attribute specification and if the entity belongs to
X-- one of the classes in the entity class list of the attribute declaration.
X-- DPS 04/23/85
X-- 
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)Ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
X  
Xpackage PACK is  
X      attribute ATE of entity is INTEGER;
Xend PACK;
X
X
X-- with package PACK;  
Xuse PACK.all;
X
Xentity E is
X    port (PT:BOOLEAN) ;
X
X      for ATE of entity E use 2;   -- Correct placement in interface declaration
X      
X--      attribute AT of body is STRING;
X      attribute AT of port, signal is BOOLEAN;
X      for AT of port PT use FALSE;
X
Xend E;
X
X
X
Xarchitecture AB of E is 
X-- DF:    block
X     
X--   for AT of body AB use "NEWER"; -- Lang Bug prohibits att_spec's for bodies
X 				    -- Attribute AT declared above
X        component COOL port (PT1:BOOLEAN) ;
X    begin
X	process
X            variable S1 : INTEGER;
X  	begin 
X     
X--        S1 <= COOL'ATE;    --Legal use, attribute both declared and specified
X    	  S1 := E'ATE;
X
X            return;
X        end process;
X--      end block;
Xend AB;    
X
Xarchitecture BB of E is 
X-- DF2:    block
X     
X    --for AT of body BB use "NEWER";-- Lang Bug prohibits att_spec's for bodies
X				    -- Attribute AT declared above
X		
X        component COOL port (PT1:BOOLEAN) ;
X
X    begin
X	process
X	  variable S1 : BOOLEAN;
X	    begin
X    
X      		S1 := PT'AT;           --Legal use, attribute both declared
X					  --and specified
X    
X-- See above 	STR := AB'AT;             --Legal use, attribute both declared
X					  --and specified
X	
X		return;
X	end process;
X
X--     end block;     
X
Xend BB;    
*-*-END-of-s-04-4-0-0001a.vhdl-*-*
echo x - s-04-4-0-0002a.vhdl
sed 's/^X//' >s-04-4-0-0002a.vhdl <<'*-*-END-of-s-04-4-0-0002a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X	--
X	--		Copyright Intermetrics 1986
X	--
X	-- 	This material may be reproduced by or for the 
X	--      U.S. Government pursuant to the copyright license 
X	-- 	under DAR clause 7-104.9(a) (1981 May)
X	--
X	--
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-04-3-2-0002A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid:  -- %G% %W% --
X-- Description:
X-- Check that all types (scalar, composite) are permitted in attribute
X-- declarations.
X-- DPS 04/21/85
X-- 
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)Ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E is
X    port (PT:BOOLEAN) ;
X      -- Scalar types, define some and used predefined ones
X      -- Enumeration....
X      type SWITCH_LEVEL is ('0','1','x','y');
X      attribute  ATSL of signal is SWITCH_LEVEL;
X      attribute ATB of signal is BOOLEAN;	 --predefined 
X      -- Integer.....  
X      type POINTER is range 0 to 31;  
X      attribute ATPT of entity is POINTER;  
X      attribute ATI of port is INTEGER;		--predefined  
X      -- Physical....  
X      type PHY is range 1 to 10
X          units
X             U;        --base unit
X             X=3U;     --other versions and conversions
X--             Y=X;
X          end units;  
X       attribute ATPHY of port, signal is PHY;  
X       attribute ATTIME of entity is TIME;      -- predefined  
X       -- Floating Point.....  
X       type FL is range 1.2 to 1.9;  
X       attribute ATREAL of port is REAL;  --predefined  
X       --Composite Types.............  
X       --Arrays  
X       type WORD is array (0 to 31) of BIT;               --constrained 
X       type INFINITE is array (INTEGER range<>) of WORD;  --unconstrained   
X       attribute ATWD of entity  is WORD;  
X       attribute ATINF of signal is INFINITE;  
X       attribute ATST of port is BIT_VECTOR;              --predefined  
X       --Records..  
X       type DATE is record  
X              DAY : INTEGER range 1 to 31;     
X              MONTH : STRING(1 To 8);  
X              YEAR : INTEGER range 1984 to 1986;      
X              end record;  
X        attribute ATDATE of entity is DATE;  
X end E;
X
X  
X       
X    
*-*-END-of-s-04-4-0-0002a.vhdl-*-*
echo x - s-04-4-0-0003a.vhdl
sed 's/^X//' >s-04-4-0-0003a.vhdl <<'*-*-END-of-s-04-4-0-0003a.vhdl-*-*'
X				
X-------------------------------------------------------------------------------
X	--
X	--		Copyright Intermetrics 1986
X	--
X	-- 	This material may be reproduced by or for the 
X	--      U.S. Government pursuant to the copyright license 
X	-- 	under DAR clause 7-104.9(a) (1981 May)
X	--
X	--
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-04-3-2-0003A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid:  -- %G% %W% --
X-- Description:
X-- Check that the same attribute can be used for several entity classes.
X-- DPS 04/23/85
X-- 
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)Ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xpackage P is
X    attribute EVERY of entity, body, function,
X                     signal, port is INTEGER;
X    -- Now use attribute EVERY for each of the entity classes
X
X    function FOO (V1:INTEGER) return INTEGER;
Xend P;
X
Xpackage body P is
X    function FOO (V1:INTEGER) return INTEGER is
X            for EVERY of function FOO use 100;  --Specify attribute for function
X    begin
X	return 1;
X    end FOO;
Xend P;
X
X  
X-- with package P;  
Xuse P.all;
Xentity E  is
X    port (PT:BOOLEAN) ;
X    for EVERY of entity E use  101;        --Specify attribute for entity
X    for EVERY of port PT use 109;          --Specify attribute for port
Xend E;
X  
Xarchitecture AB of E is 
X-- DD:block
X        signal S1: INTEGER;
X        for EVERY of signal S1 use 54;     --Specify attribute for signal
X    begin
X	process
X	begin
X	    return; 
X	end process;
X--     end block;
Xend AB;
*-*-END-of-s-04-4-0-0003a.vhdl-*-*
echo x - s-04-4-0-0004a.vhdl
sed 's/^X//' >s-04-4-0-0004a.vhdl <<'*-*-END-of-s-04-4-0-0004a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X	--
X	--		Copyright Intermetrics 1986
X	--
X	-- 	This material may be reproduced by or for the 
X	--      U.S. Government pursuant to the copyright license 
X	-- 	under DAR clause 7-104.9(a) (1981 May)
X	--
X	--
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-04-3-2-0004A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid:  -- %G% %W% --
X-- Description:
X-- Check that an attribute of an object applies to any alias of the object as 
X-- well as to the the object name declared in the object declaration.  Check
X-- for aliases which follow the attribute specification and that naming
X-- an alias in the attribute specifications entity name list.
X-- DPS 04/24/85
X-- 
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)Ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
X
Xentity Test_attributes_and_alias
X			 is
X    port ( S2 : in    integer;
X	   V2 : inout Real    ) ;
X
X    attribute V1 of port is REAL;
X    for V1 of port V2 use 1.0;
X    alias A2 : real is V2;
X
X    attribute S1 of port is INTEGER;
X    for S1 of port S2 use 1;
X    alias A1 : integer is S2;
X
Xend Test_attributes_and_alias;
X
Xarchitecture  B of Test_attributes_and_alias is
X-- SS: block
X	begin
X	 process
X            subtype BTRUE is BOOLEAN range TRUE to TRUE;
X            variable B1 : BTRUE;
X	   begin
X		if (A1'S1 = S2'S1) and (A2'V1 = V2'V1) then
X	            return;
X		end if;
X	  end process;
X--  end block;
Xend B;
*-*-END-of-s-04-4-0-0004a.vhdl-*-*
echo x - s-04-5-0-0001a.vhdl
sed 's/^X//' >s-04-5-0-0001a.vhdl <<'*-*-END-of-s-04-5-0-0001a.vhdl-*-*'
X
X-------------------------------------------------------------------------------
X	--
X	--		Copyright Intermetrics 1986
X	--
X	-- 	This material may be reproduced by or for the 
X	--      U.S. Government pursuant to the copyright license 
X	-- 	under DAR clause 7-104.9(a) (1981 May)
X	--
X	--
X-------------------------------------------------------------------------------
X-- File: %P%
X-- Original file name: S-04-4-0-0001A.VHD
X-- Version: %W% - last modified %E%
X-- sccsid:  -- %G% %W% --
X-- Description:
X-- Check that if class is not specified in a local port
X-- list then signal is assumed.
X-- DPS 04/26/85
X-- 
X-- Modification History:
X-- ---------------------------------------------------------------------------
X-- Updated to 1076-1987 VHDL, checked w/Recognizer. (Deene)Ogden@mcc.com 20jun88
X-- ***************************************************************************
X-- Begin test: >>>
X
Xentity E  is
X    port (PT:BOOLEAN) ;
Xend E;
X
Xarchitecture AB of E is
X-- B1: block
X	component A1 port (PT1 : REAL);
X	component A2 port (PT2 : INTEGER);
X        signal R : Real ;
X	signal I : Integer; 
X    begin
X	    CIS1 : A1 port (R);
X	    CIS2 : A2 port (I);
X	process
X	begin
X	    R <= 3.0;
X	    I <= 10;
X	    return;
X	end process;
X--     end block;
Xend AB;
*-*-END-of-s-04-5-0-0001a.vhdl-*-*
exit