Jari Mutikainen <Jari.Mutikainen@martis.fi> wrote in article <335CB9DB.7FE8@martis.fi>...
>
> The author recommended using TWO cascaded flip-flops for the synchroni-
> sation. This is the sure fire technique I was taught 7 years ago,
> when I first started designing digital ASICs.
> Currently I think though, that the TWO cascaded flip-
> flops for this purpose is an overkill and I use only one instead.
>
> Am I risking something here by doing so ?
>
> I think two flip-flops are needed only if the clock period of the
> synchronous system is so short, that it is close to the metastability
> time of a flip-flop. Am I correct ? Or are there any other aspects,
> that I should be aware of ?
>
> I have a gut feeling, that this metastability time of a flip-flop
> in any 'modern' ASIC technology is something like 5 ns at most.
> Does anyone know, if this a valid assumption ?

Jari, I look forward to reading the replies you get on this question
because I am doing a design where there are two separare clock
domains (same clock frequency but not synchronized) and data
has to be passed back and forth between the two.

Let me share with you some info from a book I have called "High
Speed Digital Design -- A Handbook of Black Magic" by Johnson
and Graham. According to this book, there is no such thing as
the "metastability time" that you refer to. The length of time can
be arbitrarily long (I'm not quite sure if there is a hard limit you can
guarantee for a flip flop -- maybe we'll find out). From the book:
"As the data moves toward the critical switching boundary, the Q
output still switches high, but the clock to Q delay gets longer.
For data arrivals very close to the critical switching point, the clock
to Q delay is proportional to the logarithm of the difference between
the data setup time and the critical switching point".

They go on to derive an equation for the probability of failure P (meaning
that the clock to Q delay is longer than the clock period) and based
on that, the Mean Time Between Failures (MTBF) based on the frequency
of the clock and the input transition rate. It turns out that these equations
are highly dependent on what is called the K value of the flip-flop which
is the amplifier response time constant. The higher the K value, the
smaller P is. Flip Flop designers make K as large as possible, but
there is only so far they can go with it. They do an example with an
Actel (1989) ACT1 FPGA flip flop whose K=4.6E9. At 35MHz, with input
transition rate at 1/10th the clock rate (3.5E6 transitions per second),
the MTBF is 19 hours (about once a day)!!!!

But, what happens when you cascade two flip flops in series as is
recommended. The probablility of failure now becomes P*P where
P is the probability of failure for just one flip flop. Using all the same
numbers as above, the MTBF goes from 19 hours to half a million
centuries! This drastic difference comes from squaring the probability
of 4E-12 to get 1.6E-23.

So your question really is, have the K values of modern ASIC flip flops
gotten so good that this squaring effect of adding the second flip flop
becomes unnecessary to get very high MTBF numbers?

--
Rich Iachetta
IBM Corporation
iachetta@vnet.ibm.com