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-- One-Bit RAM as a network of Bi-Directional Switches
--
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LIBRARY std;
USE std.standard.ALL;
USE work.std_logic.ALL;

ENTITY ram1 IS
  PORT ( d, db     : INOUT t_wlogic;
         rwd, rwdb : IN    t_wlogic );  -- Read/Write Control
END ram1;

ARCHITECTURE ram1_bxfr OF ram1 IS
COMPONENT nfet
  GENERIC ( gdelay      : time := 3 ps;
            MaxStrength : t_strength := 'R');
  PORT ( g        : IN    t_wlogic;
         src, drn : INOUT t_wlogic);
END COMPONENT;

COMPONENT pfet
  GENERIC ( gdelay      : time := 3 ps;
            MaxStrength : t_strength := 'R');
  PORT ( g        : IN    t_wlogic;
         src, drn : INOUT t_wlogic);
END COMPONENT;

SIGNAL s1, s2  : t_wlogic;
SIGNAL vdd : t_wlogic := F1;
SIGNAL gnd : t_wlogic := F0;

BEGIN

  vdd <= F1;
  gnd <= F0;


  i1 : nfet PORT MAP ( g=>rwd, src=>d, drn=>s1);
  i2 : nfet PORT MAP ( g=>s1, src=>s2, drn=>gnd);
  i3 : pfet PORT MAP ( g=>s1, src=>vdd, drn=>s2);
  i4 : pfet PORT MAP ( g=>s2, src=>vdd, drn=>s1);
  i5 : nfet PORT MAP ( g=>s2, src=>s1, drn=>gnd);
  i6 : nfet PORT MAP ( g=>rwdb, src=>db, drn=>s2);

END ram1_bxfr;