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-- pfet model
------------------------------
LIBRARY std;
USE std.standard.ALL;
USE work.std_logic.ALL;

ENTITY pfet IS
  GENERIC ( gdelay      : time := 3 ps;
            MaxStrength : t_strength := 'R');
  PORT ( g        : IN    t_wlogic;
         src, drn : INOUT t_wlogic);
END pfet;

ARCHITECTURE pfet_behave OF pfet IS
COMPONENT bxfr
  GENERIC ( gdelay      : time := 3 ps;
            MaxStrength : t_strength := 'R');
  PORT ( g        : IN    t_wlogic;
         src, drn : INOUT t_wlogic);
END COMPONENT;
SIGNAL tg : t_wlogic;
BEGIN
  tg <= f_logic(f_not(f_state(g)))('R');
  i1 : bxfr
       GENERIC MAP ( gdelay, MaxStrength)
       PORT MAP (tg, src, drn);
END pfet_behave;