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-- Half-Adder a network of NAND gates
--
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LIBRARY std;
USE std.standard.ALL;
USE work.std_logic.ALL;

ENTITY h_adder IS
  PORT ( a, b : IN    t_wlogic;
         sum  : INOUT t_wlogic );
END h_adder;

ARCHITECTURE h_adder_behave OF h_adder IS
COMPONENT nand2
  PORT ( a, b : IN    t_wlogic;
         z    : INOUT t_wlogic );
END COMPONENT;

SIGNAL s1, s2, s3  : t_wlogic;

BEGIN

  i0 : nand2 PORT MAP ( a, b, s1);
  i1 : nand2 PORT MAP ( a, s1, s2);
  i2 : nand2 PORT MAP ( b, s1, s3);
  i3 : nand2 PORT MAP ( s2, s3, sum);

END h_adder_behave;