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-- Full-Adder a network of NAND gates
--
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LIBRARY std;
USE std.standard.ALL;
USE work.std_logic.ALL;

ENTITY f_adder IS
  PORT ( a, b, cin : IN    t_wlogic;
         sum, cout : INOUT t_wlogic );
END f_adder;

ARCHITECTURE f_adder_behave OF f_adder IS
COMPONENT nand2
  PORT ( a, b : IN    t_wlogic;
         z    : INOUT t_wlogic );
END COMPONENT;

SIGNAL s1, s2, s3, s4, s5, s6, s7  : t_wlogic;

BEGIN

  i0 : nand2 PORT MAP ( a, b, s1);
  i1 : nand2 PORT MAP ( a, s1, s2);
  i2 : nand2 PORT MAP ( b, s1, s3);
  i3 : nand2 PORT MAP ( s2, s3, s4);
  i4 : nand2 PORT MAP ( s4, cin, s5);
  i5 : nand2 PORT MAP ( s5, cin, s6);
  i6 : nand2 PORT MAP ( s5, s4, s7);
  i7 : nand2 PORT MAP ( s6, s7, sum);
  i8 : nand2 PORT MAP ( s1, s5, cout);

END f_adder_behave;