------------------------------------------------------------------ -- PLA example -- ------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; entity pla is port ( test_vector : in std_logic_vector (3 downto 0); result_vector : out std_logic_vector (2 downto 0) ); end pla; architecture behave of pla is type std_logic_pla is array (natural range <>, natural range <>) of std_logic; procedure pla_table ( constant invec : in std_logic_vector; signal outvec : out std_logic_vector; constant table : in std_logic_pla ) is variable x : std_logic_vector (table'range(1)) ; -- product lines variable y : std_logic_vector (outvec'range) ; -- outputs variable b : std_logic ; begin assert (invec'length + outvec'length = table'length(2)) report "Size of Inputs and Outputs do not match table size" severity ERROR ; -- Calculate the AND plane x := (others=>'1'); for i in table'range(1) loop -- PLA Table ROWs for j in invec'range loop b := table (i,table'left(2)-invec'left+j) ; if (b='1') then x(i) := x(i) AND invec (j) ; elsif (b='0') then x(i) := x(i) AND NOT invec(j) ; end if ; -- If b is not '0' or '1' (e.g. '-') product line is insensitive to invec(j) end loop ; end loop ; -- Calculate the OR plane y := (others=>'0') ; for i in table'range(1) loop for j in outvec'range loop b := table(i,table'right(2) - outvec'right+j) ; if (b='1') then y(j) := y(j) OR x(i); end if ; end loop ; end loop ; outvec <= y ; end pla_table ; constant pos_of_fist_one : std_logic_pla (4 downto 0, 6 downto 0) := ( "1---000", -- first '1' is at position 0 "01--001", -- first '1' is at position 1 "001-010", -- first '1' is at position 2 "0001011", -- first '1' is at position 3 "0000111" ) ;-- There is no ¡®1¡¯ in the input begin -- Now use the pla table procedure with PLA pos_of_first_one -- test_vector is the input of the PLA, result_vector the output. pla_table ( test_vector, result_vector, pos_of_fist_one) ; end behave;