SOPC World 2007: Agenda and Technical Sessions

Note: Agenda of SOPC World Delhi will have slight modifications.

Morning Session

The New Frontier

We're entering a new frontier of system design. System complexity continues to rise dramatically; product lifecycles are shorter than ever, and time-to-profit timelines keep shrinking. For every project, you must not only meet technical goals, but also business goals that have significant impact.

To meet these goals, you need to act swiftly to continually introduce new capabilities and features while raising performance over the life of your product. And, of course, you have to accomplish all of this while keeping costs at a minimum.

In this high-pressure environment, what matters most are the choices you make at the start of every design project. Among other things, you must choose the design tools, the concept-to-production silicon strategy, the intellectual property (IP), and the level of support.

Ultimately, these choices will spell success or failure. To help you make these choices, SOPC World 2007 offers key technical sessions providing useful tips to help you strengthen your competitive edge:

• Integrating programmable solutions into a variety of industry applications
• Applying digital signal processing (DSP) and embedded technologies in FPGA designs
• Meeting signal integrity and channel optimization requirements when designing with transceiver-based FPGAs
• Lowering power consumption while optimizing performance at 65 nm

Reduce Your System Power Consumption with Altera FPGAs

In systems ranging from wireless basestations to mobile multimedia players to flat-panel TVs, requirements for ever-increasing speed, new capabilities, form-factor shrinkage, and battery life extension continue to pose big challenges to system designers. This presentation highlights the array of innovative power reduction methodologies in device architecture, new process technologies, and design software optimization that Altera has implemented in their new, 65-nm products.

Afternoon Session—Solutions Track

Leverage Altera Programmable Solutions in Industrial Applications

The industrial sector is one of the fastest growing markets for programmable logic devices. Because they enable fast time-to-market and low-cost, flexible solutions, Altera programmable solutions are being integrated into a growing array of industrial designs. From programmable logic controllers (PLCs) and I/O modules to servo drives and motion controllers, products based on programmable technology can be quickly modified to support new functionalities or requirements.

This presentation discusses Altera's complete solutions supporting industrial Ethernet applications such as motor controls and graphical controllers for human-machine interfaces (HMI).

Develop a Display System Using New Low-Cost FPGAs

High-definition television (HDTV) is proving to be a great application for today's display technologies, but the challenge has been to achieve high resolution, which requires faster data rates. Accelerating data rates requires special image-processing algorithms to support faster moving video. The industry is confronted with a major problem: how can we implement these algorithms and get a product out to market first, and do it within a known power budget?

In this presentation, you'll learn how Altera Cyclone III FPGAs:

• Offer an unprecedented combination of low power, high functionality, and low cost to enable you to design for new display applications such as
  • SD to HD conversion
  • Image enhancement
  • Timing control
• Provide application-optimized features to lower your system and development costs, including
  • Up to 4 Mbit of embedded memory
  • Up to 288 embedded 18 x 18 multipliers
  • Dynamically reconfigurable phase-locked loops (PLLs) for changing refresh rates
  • Dedicated external memory interfaces for DDR, DDR2, and QDR II at up to 400 Mbps
• Are supported by a complete design environment including
  • Video and image processing IP suite with nine common functions
  • High-performance up-scaling and video compression solution
  • Low-cost development kits
  • Quartus^® II and SOPC Builder design software

Deliver Femtocell Basestations Quickly and Cost Effectively with Altera HardCopy ASICs

Femtocell basestations are seen as an enabling technology for mobile network operators in enhancing service coverage for home and small office/home office (SOHO) users. Using femtocell basestations, mobile service providers strive to improve call quality for end users (and, in doing so, reduce their churn rate), reduce network operating expenses, and access the lucrative "last mile" market. For femtocell basestation equipment developers and manufacturers, achieving fast time to market, high performance, and low cost are paramount for success. This presentation gives an overview of the technical and business challenges of building a femtocell basestation, and shows how Altera HardCopy ASICs can be an excellent solution in addressing those challenges.

Afternoon Session—Embedded and DSP Track

Enable New Low-Cost Embedded Systems Using Cyclone III FPGAs

The evolution of embedded products creates a constant demand for new features, higher performance, and lower costs. Each of these elements poses unique challenges to the system designer. Join us in this seminar session where we will illustrate how Altera's latest 65-nm Cyclone III FPGA family, coupled with the industry-leading Nios^® II embedded processor and Quartus II design software platform, enables the realization of low cost, high performance, and high functionality in your system design.

Enhance System Performance and Productivity by Leveraging DSP and Embedded Technologies in FPGA Designs

Digital signal processing (DSP) and embedded technology based on FPGAs have been increasingly applied in system designs. They offer high performance and flexibility as well as productivity for many of today's most challenging applications, ranging from intermediate frequency (IF) modems to high-performance computing to H.264 encoding. During this technical session, several DSP-related and embedded-related tactical skills like DSP coprocessing, using C2H tools, and applying new Quartus II software features will be highlighted to help enhance the prowess of PLD designers.

Model-Based Design for Video/Image Processing Applications by The MathWorks

Model-based design is a methodology for designing embedded hardware and software systems. Due to the complexity of modern embedded systems, including video and image systems, model-based design provides a platform to perform high-level design exploration and optimizations and a formal model to support and verify the application at design time.

This tutorial explores model-based design and shows how MATLAB and Simulink from The MathWorks, together with Altera's DSP Builder, dramatically shorten design time and produce optimized implementations in Altera FPGAs. The presenter will demonstrate the design process for a video de-interlacer/scaler algorithm that can make standard-definition television look cleaner and more appealing when viewed on a high-definition screen.

Afternoon Session—High-Performance Track

Designing with 6.375-Gbps Transceiver-Based FPGAs

High-speed serial I/O protocols such as PCI Express, Serial RapidIO^®, and Gigabit Ethernet are being adopted to enable next-generation systems across different market segments, such as communications, medical, industrial, broadcast, test and measurement, storage, and military. To support such systems, FPGAs such as Stratix^® II GX devices offer embedded transceiver blocks that sustain data rates up to 6.375 Gbps. This presentation provides an in-depth analysis of challenges around designing with 6.375-Gbps transceivers, including signal integrity and channel optimization, protocol implementation, board layout techniques, and hardware verification. The presentation also provides an overview of the solutions available from Altera that help overcome these challenges.

Designing Next-Generation DDR3-Based Memory Interfaces

DDR signaling is the most common interface used in memory modules and external memory devices in the industry today. DDR3 is the next evolutionary step in memory technology and is expected to become the memory interface of choice in next-generation systems over the next few years. This presentation highlights several challenges in interfacing to DDR3 memory interfaces, such as timing margins, I/O delays, process, voltage, and temperature (PVT) variations, dynamic compensation, board layout issues, and software design flow. An overview of the Altera DDR3 solution will also be provided, with emphasis on the ALTMEMPHY intellectual property core that simplifies overall system design.

Optimizing Performance Using 65-nm Architecture

Many FPGA vendors have started shipping 65-nm FPGAs. Along with adopting the 65-nm technology, the latest FPGAs offer many innovative architectural features such as embedded memory, DSP blocks, high-speed I/O, Programmable Power Technology, PLLs, and dynamic on-chip termination (OCT). For the system designer, using these features effectively to optimize performance presents a challenge. This presentation will highlight the different architectural innovations in 65-nm FPGAs and discuss how a system designer can optimize performance. This discussion also includes an overview on achieving timing closure.

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