Packages

IEEE VHDL'87/VHDL'93 SYNOPSYS proprietary draft math std_logic_1164.vhd (ieee) standard.vhd (std) std_logic_arith.vhd    (ieee) mathpack.vhd numeric_std.vhd    (ieee) textio.vhd  (std) std_logic_misc.vhd     (ieee)   numeric_bit.vhd    (ieee)   std_logic_signed.vhd   (ieee)       std_logic_unsigned.vhd (ieee)       std_logic_textio.vhd   (ieee)       attributes.vhd     (synopsys)

Numeric Packages

• Numeric packages have been defined to support arithmetic operations on binary vectors. The IEEE packages numeric_std and numeric_bit provide the two types unsigned and signed, the latter in 2's complement number representation. The difference is that numeric_std uses vectors the components of which are of type std_logic while numeric_bit uses vectors of bit-type components.
• Package std_logic_arith is a proprietary stopgap developed by SYNOPSYS before the IEEE packages became available. It should not be used for new designs any longer now that there is an official IEEE standard.

Types in Binary Arithmetic Operations   numeric_std std_logic_arith Argument 1 Argument 2 Result unsigned unsigned unsigned unsigned/std_logic_vector unsigned integer unsigned unsigned/std_logic_vector integer unsigned unsigned unsigned/std_logic_vector signed signed signed signed/std_logic_vector signed integer signed signed/std_logic_vector integer signed signed signed/std_logic_vector

numeric_std std_logic_arith Type Conversion std_logic_vector    -> unsigned unsigned(arg) unsigned(arg) std_logic_vector    -> signed signed(arg) signed(arg) unsigned            -> std_logic_vector std_logic_vector(arg) std_logic_vector(arg) signed              -> std_logic_vector std_logic_vector(arg) std_logic_vector(arg) integer             -> unsigned to_unsigned(arg,size) conv_unsigned(arg,size) integer             -> signed to_signed(arg,size) conv_signed(arg,size) unsigned            -> integer to_integer(arg) conv_integer(arg) signed              -> integer to_integer(arg) conv_integer(arg) integer             -> std_logic_vector integer -> unsigned/signed ->std_logic_vector std_logic_vector    -> integer std_logic_vector -> unsigned/signed ->integer unsigned + unsigned -> std_logic_vector std_logic_vector(arg1 + arg2) arg1 + arg2 signed + signed     -> std_logic_vector std_logic_vector(arg1 + arg2) arg1 + arg2 Resizing unsigned resize(arg,size) conv_unsigned(arg,size) signed resize(arg,size) conv_signed(arg,size)

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Source: https://www.dz.ee.ethz.ch/en/information/hdl-help/vhdl-sources.html