--
-- Rcsid[] = "$Id: mcdecode.vhd,v 2.1 1993/10/06 01:04:36 alex Exp $";

--
-- mcdecode.vhd
-- May 22, 1993
--

-- decoding logic
--
--  This module decodes the instruction in the IR and generates
--  the signal m5reset to reset the M5 state machine at the
--  appropriate time.  It generate the signals 'wrinm2'(write
--  in M2),'wrinm3'(write in M3), and 'lastmc' (last machine
--  cycle of the instruction) etc.

--  It generates the 'onemc' signal if the instruction in the
--  instruction register is of a type that has one machine cycle.

--  A 'CC6' signal is generated if the instruction in the IR
--  has 6 T states in the first machine cycle.

entity mcdecode is
port(m5reset,wrinm2,wrinm3,lastmc,rstn,CC6: out bit;
	 ID: bit_vector (19 downto 0);
     CC,CCbar,I2,I3,I5,M1,M2,M3,M4,M5,INA: in bit);
end;

architecture structure of mcdecode is

signal n1,  n2,  n3,  n5,  n6,  n7,  JC, CC_adr, POP: bit;
signal n10, n10a,n11, n12, n12a,n13, LXI, n15, n16, n17 : bit;
signal n20, n43, n44, n47: bit;
signal n30, n32, n37, n38, n39: bit;
signal n23, n26, n29, n30a,n40: bit;
signal rstn_buf, threemc, fourmc, check1 : bit;
signal wrinm2m3, n101, n102, M6, CALL, CCond, XTHL: bit;
signal p1, p2, p3, p4, p5, PCHL, SPHL, p8, p9: bit;
signal p11, p13, p14, p15, p17, p18, p19: bit;
signal p20, INX_DCX, p21, PUSH, onemc: bit;

begin
-- JMP addr  IN port ,OUT port
U1 : and_gate generic map(2,2) port map(n1,ID(11),ID(10),ID(8));
U2 : and_gate generic map(2,2) port map(n2,ID(1),ID(5));
U3 : and_gate generic map(2,2) port map(n3,ID(0),ID(4));
U5 : and_gate generic map(2,2) port map(n5,ID(14),ID(15));
U6 : and_gate generic map(2,2) port map(n6,ID(4),ID(6),ID(5));
U7 : or_gate generic map(1,1) port map(n7,ID(19),ID(3),n1);    -- JMP/OUT/IN
U71 : or_gate generic map(1,1) port map(JC,ID(19),ID(2));      -- J cond addr
U72 : or_gate generic map(1,1) port map(CC_adr,ID(19),ID(4));  -- C cond addr
U8  : or_gate generic map(1,1) port map(POP,ID(19),ID(1),I3); -- POP rp
U10 : or_gate generic map(1,1) port map(n10,ID(19),ID(9),n2);  -- CALL addr RET
U10a : AND_gate port map(n10a,n10,n11);
-- JC/CC addr  R,C/cond(?) addr
U11 : or_gate generic map(1,1) port map(n11,CCbar,ID(19),n3);
U12 : or_gate generic map(1,1) port map(n12,ID(16),ID(2),n12a); -- LHLD/SHLD addr
U12a : AND_gate port map(n12a,ID(12),ID(13),ID(14),ID(15)); -- LHLD/SHLD/LDA/STA addr
U13 : or_gate generic map(1,1) port map(n13,ID(16),ID(2),n5); -- LDA/STA addr
U14 : or_gate generic map(1,1) port map(LXI,ID(16),ID(1));      -- LXI rp/DAD
-- MVI M data -- INR M -- DCR M
U15 : or_gate generic map(1,1) port map(n15,ID(16),ID(14),n6);
U16 : or_gate generic map(1,1) port map(n16,ID(19),ID(5));      -- PUSH/CALL
U17 : OR_gate port map(n17,n44,n10a);
U20 : or_gate generic map(1,1) port map(n20,n13,M5);
U21 : nand_gate generic map(2,2) port map(threemc,
                       n7,POP,n10a,n12,XTHL,LXI,n15,JC,CC_adr,wrinm2m3);
U22 : nand_gate generic map(2,2) port map(fourmc,n17,n12,XTHL);
U23 : or_gate generic map(1,1) port map(n23,ID(10),ID(3));     -- OUT
U24 : nand_gate generic map(2,2) port map(wrinm3,n15,n23,wrinm2m3);
U25 : or_gate generic map(1,1) port map(check1,threemc,M3);
U26 : or_gate generic map(1,1) port map(n26,fourmc,M4);
U27 : and_gate generic map(2,2) port map(m5reset,check1,n26,n20,n32,n101);
U29 : or_gate generic map(2,2) port map(n29,ID(17),ID(14));     -- MOV M,r
U30 : or_gate generic map(2,2) port map(n30,ID(16),n30a,ID(2)); -- STAX B/STAX D
U30a : AND_gate port map(n30a,ID(8),ID(10));
U31 : nand_gate generic map(2,2) port map(wrinm2,n29,n30,wrinm2m3);
U32 : or_gate generic map(1,1) port map(n32,onemc,M2);
U37 : or_gate generic map(2,2) port map(n37,onemc,M1);
U38 : or_gate generic map(2,2) port map(n38,threemc,M2);
U39 : or_gate generic map(2,2) port map(n39,M3,fourmc);
U40 : or_gate generic map(2,2) port map(n40,n13,M4);
U41 : and_gate generic map(2,2) port map(lastmc,n37,n38,n39,n40,M5);
U42 : or_gate generic map(2,2) port map(rstn_buf,ID(19),ID(7));    -- RST n
U42a : buf_gate port map (rstn,rstn_buf);
U43 : and_gate generic map(2,2) port map(n43,rstn_buf,n47);
U44 : inv_gate generic map(1,1) port map(n44,I2);
U47 : inv_gate generic map(1,1) port map(n47,INA);
U50 : AND_gate port map (wrinm2m3,n16,n43);
U100 : NAND_gate port map(M6,M1,M2,M3,M4,M5);
U101 : OR_gate   port map(n101,M6,n102);
-- LHLD,SHLD,XTHL,CALL,CCond have 5 M-cycles
U102 : AND_gate  port map(n102,n12,XTHL,CALL,CCond);
U103 : OR_gate   port map(CALL,ID(19),ID(9),ID(5));
U104 : OR_gate   port map(CCond,ID(19),ID(4),CCbar); -- CALL Conditional
U110 : OR_gate   port map(XTHL,ID(19),ID(12),ID(3));   -- XTHL
V1 : inv_gate generic map(2,2) port map(p1,ID(6));
V2 : AND_gate generic map(2,2) port map(p2,ID(8),ID(12),ID(14));
V3 : inv_gate generic map(2,2) port map(p3,ID(14));
V4 : inv_gate generic map(2,2) port map(p4,ID(12));
V5 : or_gate generic map(1,1) port map(p5,ID(16),ID(0),p2);
V6 : or_gate generic map(1,1) port map(PCHL,ID(19),ID(1),ID(13));
V7 : or_gate generic map(1,1) port map(SPHL,ID(15),ID(1),ID(19));
V8 : or_gate generic map(1,1) port map(p8,ID(19),ID(0),CC);
V9 : or_gate generic map(1,1) port map(p9,ID(18),p1);
V11 : or_gate generic map(1,1) port map(p11,ID(16),ID(7));
V12 : or_gate generic map(1,1) port map(INX_DCX,ID(16),ID(3));
V13 : or_gate generic map(1,1) port map(p13,ID(19),ID(3),p17,p4);
V14 : or_gate generic map(1,1) port map(p14,ID(16),p15,p3);
V15 : and_gate generic map(1,1) port map(p15,ID(5),ID(4));
V16 : and_gate generic map(4,4) port map(onemc,
                          p5,PCHL,SPHL,p8,p9,p11,INX_DCX,p13,p14,p18,p19);
V17 : inv_gate generic map(1,1) port map(p17,I5);
V18 : or_gate generic map(1,1) port map(p18,ID(17),ID(14),ID(6));
V19 : or_gate generic map(1,1) port map(p19,ID(17),p1,p3);
V20 : and_gate generic map (1,1) port map(p20,ID(0),ID(4),ID(7));
V21 : or_gate generic map (1,1) port map(p21,ID(19),p20);
V22 : nand_gate generic map (1,1) port map(CC6,INX_DCX,p21,CALL,PCHL,SPHL,PUSH);
V23 : or_gate generic map (1,1) port map(PUSH,ID(19),ID(5),I3);
end structure;

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