-- ---------------------------------------------------------------------------
-- EPLD and FPGA chip definitions -- PACKAGE --
-- ---------------------------------------------------------------------------
--
-- File : 'chips.vhd'
-- Author : Lars Larsson
--
-- Date : Feburary 5, 1999
--
-- ---------------------------------------------------------------------------
--
-- Copyright (C) 1998 Lars Larsson, Dept. of Computer Science
-- University of Hamburg
-- Vogt-Koelln-Str. 30
-- D - 22041 Hamburg, Germany
-- larsson@informatik.uni-hamburg.de
-- http://tech-www.informatik.uni-hamburg.de/~larsson
--
-- This program is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at your
-- option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
--
-- ---------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package chips is
-- -------------------------------------------------------------------------------
type ram_type is ( SRAM, DRAM ); -- RAM_TYPE <= { SRAM, DRAM }
-- -------------------------------------------------------------------------------
component epld
port(
clk : in std_ulogic; -- clock = 16 MHz
nrst : in std_ulogic; -- *reset
--
baud_rate_select : in std_ulogic_vector (2 downto 0); -- baud rate selection
nsend_receive : in std_ulogic; -- send/receive selection (0:send,1:receive)
--
rs232_txd : in std_ulogic; -- TXD signal (TTL) from RS232
rs232_rxd : out std_ulogic; -- RXD signal (TTL) to RS232
irda_rxda : in std_ulogic; -- RXD-A (IrDA 1.0) signal from HSDL-1100
irda_txd : out std_ulogic; -- TXD (IrDA 1.0 & 1.1) signal to HSDL-1100
--
nkey : in std_ulogic; -- strobe key (push down = '0', up = '1')
dip_switches : in std_ulogic_vector ( 7 downto 0); -- DIP-Switches 1-2-3-4-5-6-7-8
--
idata : in std_ulogic_vector ( 7 downto 0); -- data bus input (if nwe+'1')
odata : out std_ulogic_vector ( 7 downto 0); -- data bus output (if nwe='0')
address : out std_ulogic_vector (10 downto 0); -- address bits A10 downto A0 for SRAM xOR DRAM
nwe : out std_ulogic; -- read / write selector for RAM (not write enable)
--
ncs : out std_ulogic; -- not Chip Select of SRAM
--
nras : out std_ulogic; -- not Row Address Strobe (nRAS) of DRAM
ncas : out std_ulogic; -- not Column Address Strobe (nCAS) of DRAM
type_of_ram : out ram_type -- {SRAM,DRAM}
);
end component;
component epld_buffered -- same as 'epld' but with 'text_buffer'
port(
clk : in std_ulogic; -- clock = 16 MHz
nrst : in std_ulogic; -- *reset
--
baud_rate_select : in std_ulogic_vector (2 downto 0); -- baud rate selection
nsend_receive : in std_ulogic; -- send/receive selection (0:send,1:receive)
--
rs232_txd : in std_ulogic; -- TXD signal (TTL) from RS232
rs232_rxd : out std_ulogic; -- RXD signal (TTL) to RS232
irda_rxda : in std_ulogic; -- RXD-A (IrDA 1.0) signal from HSDL-1100
irda_txd : out std_ulogic; -- TXD (IrDA 1.0 & 1.1) signal to HSDL-1100
--
nkey : in std_ulogic; -- strobe key (push down = '0', up = '1')
dip_switches : in std_ulogic_vector ( 7 downto 0); -- DIP-Switches 1-2-3-4-5-6-7-8
--
idata : in std_ulogic_vector ( 7 downto 0); -- data bus input (if nwe+'1')
odata : out std_ulogic_vector ( 7 downto 0); -- data bus output (if nwe='0')
address : out std_ulogic_vector (10 downto 0); -- address bits A10 downto A0 for SRAM xOR DRAM
nwe : out std_ulogic; -- read / write selector for RAM (not write enable)
--
ncs : out std_ulogic; -- not Chip Select of SRAM
--
nras : out std_ulogic; -- not Row Address Strobe (nRAS) of DRAM
ncas : out std_ulogic; -- not Column Address Strobe (nCAS) of DRAM
type_of_ram : out ram_type -- {SRAM,DRAM}
);
end component;
component epld_glue
port(
clk : in std_ulogic; -- clock = 16 MHz
nrst : in std_ulogic; -- *reset
--
baud_rate_select : in std_ulogic_vector (2 downto 0); -- baud rate selection
nsend_receive : in std_ulogic; -- send/receive selection (0:send,1:receive)
--
rs232_txd : in std_ulogic; -- TXD signal (TTL) from RS232
rs232_rxd : out std_ulogic; -- RXD signal (TTL) to RS232
irda_rxda : in std_ulogic; -- RXD-A (IrDA 1.0) signal from HSDL-1100
irda_txd : out std_ulogic; -- TXD (IrDA 1.0 & 1.1) signal to HSDL-1100
--
nkey : in std_ulogic; -- strobe key (push down = '0', up = '1')
dip_switches : in std_ulogic_vector ( 7 downto 0); -- DIP-Switches 1-2-3-4-5-6-7-8
--
idata : in std_ulogic_vector ( 7 downto 0); -- data bus input (if nwe='1')
odata : out std_ulogic_vector ( 7 downto 0); -- data bus output (if nwe='0')
address : out std_ulogic_vector (10 downto 0); -- address bits A10 downto A0 for SRAM xOR DRAM
nwe : out std_ulogic; -- read / write selector for RAM (not write enable)
--
ncs : out std_ulogic; -- not Chip Select of SRAM
--
nras : out std_ulogic; -- not Row Address Strobe (nRAS) of DRAM
ncas : out std_ulogic; -- not Column Address Strobe (nCAS) of DRAM
type_of_ram : out ram_type; -- {SRAM,DRAM}
-- - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - - - - - - - - - - - - - -
to_flex : out std_logic; -- TriState IO contol for FLEXs
flex_iodata : inout std_logic_vector ( 7 downto 0); -- TriState bus between EPLD, FLEXA, FLEXB
flex_busy : out std_logic; -- to hold input of FLEX
flex_request : in std_logic; -- from send output of FLEX
flex_hold : in std_logic; -- from busy output of FLEX
flex_send : out std_logic -- to request input of FLEX
);
end component;
component epm7128slc84
port(
clk : in std_ulogic; -- clock = 16 MHz [16 MHz quartz oscillator]
nrst : in std_ulogic; -- *reset [automatic power-on reset]
baud_rate_select : in std_ulogic_vector (2 downto 0); -- baud rate selection [DIP-Switch 1]
nsend_receive : in std_ulogic; -- send/receive selection (0:send,1:receive) [DIP-Switches 2-3-4]
rs232_txd : in std_ulogic; -- TXD signal (TTL) from RS232 [from pin 2 of 9]
rs232_rxd : out std_ulogic; -- RXD signal (TTL) to RS232 [to pin 3 of 9]
irda_rxda : in std_ulogic; -- RXD-A (IrDA 1.0) signal from HSDL-1100 [from pin 8]
irda_txd : out std_ulogic; -- TXD (IrDA 1.0 & 1.1) signal to HSDL-1100 [via RC to HSDL-1100 pin TX(7)]
nkey : in std_ulogic; -- strobe key (push down = '0', up = '1') [key beside the DIP-SWITCH]
dip_switches : in std_ulogic_vector (7 downto 0); -- [DIP-Switches 1-2-3-4-5-6-7-8]
--
data : inout std_logic_vector (7 downto 0); -- bidirectional data bits (2Kx8 SRAM, 4Mx8 DRAM)
address : out std_ulogic_vector (10 downto 0); -- address bits A10 downto A0 of SRAM xOR DRAM
nwe : out std_ulogic; -- read / write selector for RAM (not write enable)
--
ncs : out std_ulogic; -- not Chip Select of SRAM
--
nras : out std_ulogic; -- not Row Address Strobe (nRAS) of DRAM
ncas : out std_ulogic -- not Column Address Strobe (nCAS) of DRAM
);
end component;
component epm7160slc84
port(
clk : in std_ulogic; -- clock = 16 MHz [16 MHz quartz oscillator]
nrst : in std_ulogic; -- *reset [automatic power-on reset]
baud_rate_select : in std_ulogic_vector (2 downto 0); -- baud rate selection [DIP-Switch 1]
nsend_receive : in std_ulogic; -- send/receive selection (0:send,1:receive) [DIP-Switches 2-3-4]
rs232_txd : in std_ulogic; -- TXD signal (TTL) from RS232 [from pin 2 of 9]
rs232_rxd : out std_ulogic; -- RXD signal (TTL) to RS232 [to pin 3 of 9]
irda_rxda : in std_ulogic; -- RXD-A (IrDA 1.0) signal from HSDL-1100 [from pin 8]
irda_txd : out std_ulogic; -- TXD (IrDA 1.0 & 1.1) signal to HSDL-1100 [via RC to HSDL-1100 pin TX(7)]
nkey : in std_ulogic; -- strobe key (push down = '0', up = '1') [key beside the DIP-SWITCH]
dip_switches : in std_ulogic_vector (7 downto 0); -- [DIP-Switches 1-2-3-4-5-6-7-8]
--
data : inout std_logic_vector (7 downto 0); -- bidirectional data bits (2Kx8 SRAM, 4Mx8 DRAM)
address : out std_ulogic_vector (10 downto 0); -- address bits A10 downto A0 of SRAM xOR DRAM
nwe : out std_ulogic; -- read / write selector for RAM (not write enable)
--
ncs : out std_ulogic; -- not Chip Select of SRAM
--
nras : out std_ulogic; -- not Row Address Strobe (nRAS) of DRAM
ncas : out std_ulogic; -- not Column Address Strobe (nCAS) of DRAM
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
to_flex : out std_logic; -- TriState IO contol for FLEXs
flex_iodata : inout std_logic_vector ( 7 downto 0); -- TriState bus between EPLD, FLEXA, FLEXB
flex_busy : out std_logic; -- to hold input of FLEX
flex_request : in std_logic; -- from send output of FLEX
flex_hold : in std_logic; -- from busy output of FLEX
flex_send : out std_logic -- to request input of FLEX
);
end component;
-- -------------------------------------------------------------------------------
component glue
port(
clk : in std_ulogic; -- clock = 16 MHz
nrst : in std_ulogic; -- *reset
nsend_receive : in std_ulogic; -- (0:send,1:receive)
rs232receiver_busy : out std_ulogic; -- to HOLD input of RS232 receiver/text / text buffer
rs232receiver_request : in std_ulogic; -- from send output of RS232 receiver / text buffer
rs232receiver_idata : in std_ulogic_vector ( 7 downto 0); -- from data byte output of RS232 receiver
rs232sender_hold : in std_ulogic; -- from busy output of RS232 sender
rs232sender_send : out std_ulogic; -- to request input of RS232 sender
rs232sender_odata : out std_ulogic_vector ( 7 downto 0); -- to data byte input of RS232 sender
to_flex : out std_logic; -- TriState IO contol for FLEXs
flex_iodata : inout std_logic_vector ( 7 downto 0); -- TriState bus between EPLD, FLEXA, FLEXB
flex_busy : out std_logic; -- to hold input of FLEX
flex_request : in std_logic; -- from send output of FLEX
flex_hold : in std_logic; -- from busy output of FLEX
flex_send : out std_logic -- to request input of FLEX
);
end component;
-- -------------------------------------------------------------------------------
component flexa -- Flex10K FPGA A (data compression processor)
port(
clk : in std_logic; -- clock = 16 MHz quartz oscillator
nrst : in std_logic; -- *reset (automatic power-on reset)
nsend_receive : in std_logic; -- send/receive selection (0:send,1:receive)
request : in std_logic; -- request to process (=>send)
send : out std_logic; -- start sending (=>request)
hold : in std_logic; -- hold (not enable) (=>busy)
busy : out std_logic; -- busy indicator (=>hold)
char_in : in std_logic_vector (7 downto 0); -- input data stream
char_out : out std_logic_vector (7 downto 0); -- output data stream
data_in : in std_logic; -- busy indicator
data_out : out std_logic -- busy indicator
);
end component;
component epf10k10lc84a -- Flex10K FPGA A (data compression processor)
port(
clk : in std_ulogic; -- clock = 16 MHz quartz oscillator
nrst : in std_ulogic; -- *reset (automatic power-on reset)
nsend_receive : in std_ulogic; -- send/receive selection (0:send,1:receive)
to_flex : in std_ulogic; -- define direction of data (0:read from FLEX, 1:write into FLEX)
request : in std_ulogic; -- request to process (=>send)
request_rsa : out std_ulogic; -- request to process (=>send)
send : out std_ulogic; -- start sending (=>request)
send_rsa : in std_ulogic; -- start sending (=>request)
hold : in std_ulogic; -- hold (not enable) (=>busy)
hold_rsa : out std_ulogic; -- hold (not enable) (=>busy)
busy : out std_ulogic; -- busy indicator (=>hold)
busy_rsa : in std_ulogic; -- busy indicator (=>hold)
char_inout : inout std_logic_vector (7 downto 0); -- bidirectional data stream (nsend_receive)
data_in : in std_ulogic; -- busy indicator
data_out : out std_ulogic -- busy indicator
);
end component;
component flexb -- FLEX B (RSA processor)
port(
clk : in std_logic; -- clock = 16 MHz quartz oscillator
nrst : in std_logic; -- *reset (automatic power-on reset)
nsend_receive : in std_logic; -- send/receive selection (0:send,1:receive)
request : in std_logic; -- request to process (=>send)
send : out std_logic; -- start sending (=>request)
hold : in std_logic; -- hold (not enable) (=>busy)
busy : out std_logic; -- busy indicator (=>hold)
char_in : in std_logic_vector (7 downto 0); -- input data stream
char_out : out std_logic_vector (7 downto 0); -- output data stream
data_in : in std_logic; -- busy indicator
data_out : out std_logic -- busy indicator
);
end component;
component epf10k10lc84b -- Flex10K FPGA B (RSA processor)
port(
clk : in std_ulogic; -- clock = 16 MHz quartz oscillator
nrst : in std_ulogic; -- *reset (automatic power-on reset)
nsend_receive : in std_ulogic; -- send/receive selection (0:send,1:receive)
to_flex : in std_ulogic; -- define direction of data (0:read from FLEX, 1:write into FLEX)
request : in std_ulogic; -- request to process (=>send)
send : out std_ulogic; -- start sending (=>request)
hold : in std_ulogic; -- hold (not enable) (=>busy)
busy : out std_ulogic; -- busy indicator (=>hold)
char_inout : inout std_logic_vector (7 downto 0); -- bidirectional data stream (nsend_receive)
data_in : in std_ulogic; -- busy indicator
data_out : out std_ulogic -- busy indicator
);
end component;
-- -------------------------------------------------------------------------------
end chips;
package body chips is
end chips;
-- -------------------------------------------------------------------------------
<div align="center"><br /><script type="text/javascript"><!--
google_ad_client = "pub-7293844627074885";
//468x60, Created at 07. 11. 25
google_ad_slot = "8619794253";
google_ad_width = 468;
google_ad_height = 60;
//--></script>
<script type="text/javascript" src="http://pagead2.googlesyndication.com/pagead/show_ads.js">
</script><br /> </div>