-- ---------------------------------------------------------------------------
--  IrDA - declarations for simulation                           -- PACKAGE --
-- ---------------------------------------------------------------------------
--
--  File   :   'simulation.vhd'
--  Author :    Lars Larsson
--
--  Date   :    February 15, 1998
--
-- ---------------------------------------------------------------------------
--
-- Copyright (C) 1999 Lars Larsson, Dept. of Computer Science
--                                  University of Hamburg
--                                  Vogt-Koelln-Str. 30
--                                  D - 22041 Hamburg, Germany
--                                  larsson@informatik.uni-hamburg.de
--
-- This program is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at your
-- option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
--
-- ---------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

package simulation is

   constant CLK_PERIOD : time :=  62.50 ns;  -- 16 MHz
   constant RST_DELAY  : time := 125.00 ns;  --

   constant    T_LIMIT : time :=  85.05 us;  -- fuse lock time limit
   constant    T_RELAX : time := 425.25 us;  -- fuse relaxing time


-- Some HSDL-1100 switching characteristics

   constant TPWA_MIN : time := 1.0 us;
   constant TPWA_MAX : time := 7.5 us;

   constant TPWB_MIN : time :=  75 ns;
   constant TPWB_MAX : time := 185 us;

   constant   TL_TYP : time := 0.5 ms;
   constant   TL_MAX : time := 1.0 ms;

-- ----------------------------------------

   type radiant_power is range 0 to 1000000
        units
         uW;
         mW =  1000 uW;
          W =  1000 mW;
        end units;

   type distance is range 0 to 1000000
        units
         mm;
         cm =   10  mm;
          m = 1000  mm;
        end units;
   
   type radiant_intensity is range 0 to 1000000
        units
          uW_per_SR;
          mW_per_SR = 1000 uW_per_SR;
           W_per_SR = 1000 mW_per_SR;
        end units;


   component HSDL1100
     port(    
             txd :  in std_ulogic;        -- input for signal rates from 2.4 to 115.2 Kb/s
                                          -- and for signal rates of 576 Kb/s and 4.0 Mb/s
            ledi :  in std_ulogic;        -- digital input of IR diode signal 
            ledo : out std_ulogic;        -- digital output of IR diode signal

            rxda : out std_ulogic;        -- output for signal rates from 2.4 to 115.2 Kb/s
            rxdb : out std_ulogic;        -- output for signal rates of 576 Kb/s and 4.0 Mb/s

             iro : out radiant_intensity; --  infrared light output [mW/SR]
             iri :  in radiant_intensity  --  infrared light input [mW/SR]

             -- led_status : out ledstatus;  -- status of the IR transmitter diode
             -- pin_status : out pinstatus   -- status of the receiver diode

          );
   end component;

   component sram61256
     port(     
               nwe :    in std_logic;                      -- Not Write Enable
               ncs :    in std_logic;                      -- Not Chip Select
               noe :    in std_logic;                      -- Not Output Eneble
           address :    in std_logic_vector (14 downto 0); -- ADDRESS bus
              data : inout std_logic_vector ( 7 downto 0)  -- bidirectional DATA bus 
         );
   end component;

   component board
     port(
                  clk :  in std_ulogic;  -- clock = 16 MHz
                 nrst :  in std_ulogic;  -- *reset

     baud_rate_select :  in std_ulogic_vector (2 downto 0);  -- baud rate selection
        nsend_receive :  in std_ulogic;  -- send/receive selection (0:send,1:receive)

            rs232_txd :  in std_ulogic;  -- TXD signal (TTL) from RS232
            rs232_rxd : out std_ulogic;  -- RXD signal (TTL) to RS232
            irda_rxda :  in std_ulogic;  -- RXD-A (IrDA 1.0) signal from HSDL-1100
             irda_txd : out std_ulogic;  -- TXD (IrDA 1.0 & 1.1) signal to HSDL-1100

                 nkey :  in std_ulogic;  -- strobe key (push down = '0', up = '1')
         dip_switches :  in std_ulogic_vector (7 downto 0); -- [DIP-Switches 1-2-3-4-5-6-7-8]
            led_array : out std_ulogic_vector (7 downto 0)  -- 8 x LED array (high active)
          );
   end component;

   component string2txd
     port(
               t :  in time;       -- T_BAUD = 1/(baud rate)
               s :  in string;     -- text string to send
             txd : out std_ulogic  -- RS232 TxD signal of the string 's'
         );
   end component;

   component txd2irda
     port(         
                     t :  in time;             -- T_BAUD = 1/(baud rate)
             rs232_txd :  in std_ulogic;       -- RS232 TxD signal input 
              irda_txd : out std_ulogic        -- IrDA 1.0 TXD output
          );
   end component;

   component irda2rxd
     port(         
                     t :  in time;             -- T_BAUD = 1/(baud rate)
             irda_rxda :  in std_ulogic;       -- IrDA 1.0 RxD_A input (low active)
             rs232_rxd : out std_ulogic        -- RS232 RxD output
          );
   end component;

   component rxd2char
     port(
                  t :  in time;                           -- T_BAUD = 1/(baud rate)
          rs232_rxd :  in std_ulogic;                     -- RS232 RxD signal input
                bin : out std_ulogic_vector (7 downto 0); -- binary code
                chr : out character;                      -- character
             strobe : out std_ulogic                      -- strobe signal
          );
   end component;

   component flex_handshake
     port(
              clk :    in std_logic;
             nrst :    in std_logic;
          to_flex :    in std_logic;
           iodata : inout std_logic_vector (7 downto 0);
             busy :   out std_logic;
          request :    in std_logic;
             hold :    in std_logic;
             send :   out std_logic
         );
   end component;

end simulation;

-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

-- package body simulation is 
-- end simulation;

-- -------------------------------------------------------------------------------  
  

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