These examples of syntisable designs are available on VHDL.ORG
proposed by NAVABI (navabi@ece.neu.edu)

(RTL models are available only here)

ORIGINAL ---- Behevioral definitions
RTL      ---- RTL synthesis (Y.HERVE ERM/PHASE with EXEMPLAR/CORE)
HARDWARE ---- structural (pAsic targetted)
TESTING/LIST  listfil output of tests (V-SYSTEM/MODELTECH ?)
TESTING/TEST  testbenchs 
SIM_LIB/PAsic20.VHD   gate models for structural simulation