Control flow: Finite State Machines

Mealy and Moore Machines

Mealy machine

	S(t+1) <= fa (S(t), X(t));
	Z(t)   <= ga (S(t), X(t));

Moore machine

	S(t+1) <= fb (S(t), X(t));
	Z(t)   <= gb (S(t));

The difference is that the output of the Moore machine is a function of the current state of the machine only, while the output of the Mealy machine will follow changes in the input that occur while the machine is in the current state.

The output behavior of the Moore machine is more predictable, but the design of the Mealy machine typically leads to fewer states. If we consider only the input value of the Mealy machine at the transition time to the next state, it is possible to contruct equivalent Mealy and Moore machines.

The state equations above suggest the form of the processes in VHDL that can be transformed into FSMs.

VHDL Example of a state machine

entity test is
	port (X, clock : in bit;
		Z : out bit);
end test;
architecture trial of test is
signal ST : (S0, S1, S2, S3);  --state can take one of these values.
begin
process
begin
	wait until clock'event and clock = '1';
	if X = '1' then 
		case ST is
		when S0 => ST <= S1; Z <= '0';
		when S1 => ST <= S2; Z <= '0';
		when S2 => ST <= S3; Z <= '0';
		when S3 => ST <= S0; Z <= '1';
		end case;
	else 
		Z <= '0';  -- and ST does not change
	end if;
end process;
end trial;

Note: Synthesis tools such as Synopsys DC infer that state does not change if not specified since no event is produced to change the value of the state signal.

It is natural to want to separate the state transition function from the output function. If one recognizes the counter in the example above, it leads one to write the following concurrent VHDL realization:

	ST <= COUNT (ST) when X = '1' ;
	Z <= '1' when ST = S3 else '0';

(This assumes we want the states S0-S3 to be numbered consecutively 00 01 10 11.)

Separating the combinational logic from the flipflops

It is possible to separate the combinational logic from the sequential elements, and this makes the synthesis process more straightforward and predictable.

entity test is
	port (X, clock : in bit;
		Z : out bit);
end test;
architecture trial of test is
type state : (S0, S1, S2, S3);  --state can take one of these values.
signal CURRENT_STATE, NEXT_STATE : state;
    -- special vendor-defined attribute recognized by Synopsys DC
    -- defining the signal to be treated as holding the state value.
    attribute STATE_VECTOR : string;
    attribute STATE_VECTOR of trial : architeture is "CURRENT_STATE";
begin
process ( CURRENT_STATE, X)  -- combinational logic for NEXT_STATE and Z
begin
	if X = '1' then 
		case CURRENT_STATE is
		when S0 => NEXT_STATE <= S1; Z <= '0';
		when S1 => NEXT_STATE <= S2; Z <= '0';
		when S2 => NEXT_STATE <= S3; Z <= '0';
		when S3 => NEXT_STATE <= S0; Z <= '1';
		end case;
	else 
		Z <= '0';
		NEXT_STATE <= CURRENT_STATE;
	end if;
end process;
SYNCH: process 
begin
	wait until clock'event and clock = '1';
	CURRENT_STATE <= NEXT_STATE;
end process;

end trial;

Enumerated types and explicit encoding directives

Frequently the state ordering that is natural from a specification perspective is not the most efficient encoding from the standpoint of logic optimization. If the synthesis tool uses the integer ordering of the enumerated type instead of applying an algorithm for optimal state assignment (see Story, et als., IEEETC, Dec. 1972), you will want to provide an explicit encoding directive.

For example, suppose we wish to use Gray code encoding for the counter above. For the Synopsys DC synthesis tool you would use the ENUM_ENCODING attribute as follows:

entity test is
	port (X, clock : in bit;
		Z : out bit);
end test;
architecture trial of test is
type state : (S0, S1, S2, S3);  --state can take one of these values.
    attribute ENUM_ENCODING : string;
    attribute ENUM_ENCODING of state : type is "00 01 11 10";
signal CURRENT_STATE, NEXT_STATE : state;

Rev. 9/16/95 B. Huey