CSE 591: Synthesis with Hardware Description Languages
Laboratory Assignment #1

Due date: September 20, 1995

Objectives:

1. Familiarization with Mentor Graphics Design Manager and Design Architect.
2. Familiarization with Mentor Graphics on-line documentation and browsing tool.
3. Practice with VHDL design capture and QuickVHDL simulation.
4. Review of VHDL concepts.

Reference sources:

• Mentor Design Manager and Design Architect tutorials.
• Mentor Sys_1076 tutorial (VHDL and simulation).
• Perry: VHDL

Project:

1. Create a design entity for a four function logic unit with std_logic consisting of:

   Vector inputs X and Y.

   A 3 bit function selector input Func_Sel(0 to 2)

   A positive edge trigger clock

   Vector output Z.

   This is to be an N-bit wide unit, so declare the width to be a generic, and include assertions to check that the connecting bus attributes correspond.

   Also include a generic for timing values Tgate, gate propagation delay, and Treg, output register propagation delay.

2. Create an architecture using only concurrent VHDL constructs to implement the following functions:

   	Func_sel	Operation
   	000		Z <= X
   	001		Z <= NOT X
   	010		Z <= X AND Y
   	011		Z <= X NAND Y
   	100		Z <= X OR Y
   	101		Z <= X NOR Y
   	110		Z <= X XOR Y
   	111		Z <= X XNOR Y
   

   All the logic in this part of your design will be assumed to have input-output propagation delay of Tgate.

   There is to be an "accumulator" register to receive the result of the function computation and drives the output Z, with propagation delay Treg.

3. Instantiate the design with N=4 and simulate it to verify that it works correctly.

4. Create a new architecture for the same entity using only structural VHDL.
   To do this part of the design first create a separate logic_slice entity with a single bit wide implementation of the architecture above instantiated N times with a FOR - GENERATE. Optimize the design by creating a separate function enable for each of the eight functions and drive all of the N slices from a single decode unit. Estimate how many gates this saves. What is the effect on timing?

5. Repeat the simulation.

Report

In your report include:

1. For the concurrent architecture:

   a. Compiled VHDL listing of the design

   b. Description of the Design Architect, Design Manager, VHDL compiler and simulator commands use to complete the design and simulation.

   c. Listing of the commands issued to the simulator and listing of the responses.

2. For the structural architecture:

   a, b, and c as above.

   d. Discussion of the optimization performed and estimate of the benefits / penalties involved.

Revised 12/11/95